Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

Abstract: The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.

Abstract: Methods are provided for transforming a declarative description of a processor of the packets of a communication protocol. A first declarative description of the packet processor is input. The first declarative description includes rules that include actions for manipulating the fields of the packets. Each rule includes one or more of the actions, and at least one of the rules includes multiple actions and a guard condition for enabling and disabling some of these actions. The first declarative description is transformed into a second declarative description of the packet processor. The second declarative description includes rules for manipulating the fields of the packets, and each rule corresponds to an action of a rule of the first declarative description. In addition, each individual action of each rule of the first declarative description corresponds to a rule of second declarative description that includes the individual action. The second declarative description is output.

Abstract: An amplifier circuit having a differential input and an amplifier output is provided. In some examples, the amplifier circuit includes a first input stage having a first complementary transistor pair providing a first input and a first output, the first input being a first half of the differential input; a second input stage having a second complementary transistor pair providing a second input and a second output, the second input being a second half of the differential input; an output stage coupled to the first input stage and the second input stage and providing the amplifier output; and a transistor coupled in parallel to one transistor in one of the first complementary transistor pair or the second complementary transistor pair.

Abstract: A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.

Abstract: A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits and data enable bits are bitwise ANDed to provide interim data outputs. The interim data outputs are XORed to provide resultant data outputs. The resultant checksum outputs and the resultant data outputs are bitwise XORed to provide parity outputs.

Abstract: An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Abstract: A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (1130). The method can include, responsive to detecting the deadlock state, adjusting the at least one control bit within a current frame (1135). Adjusting the at least one control bit clears the deadlock state and generates a modified frame. The modified frame can be output to at least one node within the network (1140).

Abstract: A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and cannot compare differences between models created with third party design environments. The present invention increases interoperability and capabilities of existing circuit design environments, and achieves an advance in the art, by converting high level block diagram models to a user readable text-based format and performing a text-based differential analysis on the converted models to determine differences.

Abstract: A system detects a communication transmitted from multiple transmitting antennas. The system includes a media access controller and a physical block. Based on a signal to noise ratio (SNR), the allocation circuit of the media access controller assigns a portion of a spectral resource to the communication. The physical block includes multiple receiving antennas for receiving the communication, an estimating circuit for determining the SNR of the communication received at the receiving antennas, and a sphere detector. The sphere detector calculates a respective cost for possible combinations of symbols for the transmitting antennas. The sphere detector calculates the respective costs of the possible combinations from the portion of the spectral resource of the communication received at the receiving antennas. The sphere detector selects one of the possible combinations in response to the respective costs. The system detects the transmitted communication to be the symbols of the selected combination.

Abstract: A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. The first PNS library can be correlated with a first die of the IC. The second PNS library can be correlated with the second die of the IC. Via a processor, a circuit element can be defined within a circuit design implemented within the IC according to the PNS library correlated to the die in which the circuit element is located.

Abstract: A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a first inverter comprising a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter comprising a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the second node being coupled to a control terminal of the second transistor. The memory array further comprises a third inverter and a fourth inverter.

Abstract: One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Abstract: For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.

Abstract: A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer.

Abstract: An integrated circuit (“IC”) (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2, RA3, RA4) are compared (102) to corresponding registers of the second instantiation (RB1, RB2, RB3, RB4). If a register pair does not match, the user designs are halted, re-loaded, and re-started.

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract: A method for optimizing a high-level circuit architecture for an integrated circuit is described. Descriptions of components of the circuit architecture and optimization goals for the components are received. At least one stopping criterion for the cost functions is received. Implementations for the components are iteratively generated to provide a system from a combination of the implementations. The implementations of the components are iteratively optimized until the at least one stopping criterion is satisfied. The optimizing includes obtaining estimation models for determining cost estimates for the implementations and iteratively optimizing the implementations responsive to the cost estimates.