Abstract: An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected.

Abstract: An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement.

Abstract: Determining a sum of absolute differences using a circuit is described. Pairs of inputs, including a respective current value and a respective previous value, are obtained. The previous value is subtracted from the current value for each of the pairs of inputs to provide differences and associated carries. Inverted carries are applied to the differences to pass a first portion of the differences associated with positive absolute differences and to invert and then pass a second portion of the differences associated with negative absolute differences. The inverted carries are summed. The first portion and the second portion are provided to an adder tree to generate an interim sum of absolute differences. The sum of inverted carries obtained over a number of clock cycles is added to the interim sum of absolute differences obtained over the number of clock cycles to generate a sum of absolute difference result.

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: Approaches for generating a specification of a pipelined packet processor. A textual specification includes input and output packet formats, each specifying a format for each field in the packet and a plurality of actions for processing one or more fields of an input packet. Pipeline stages are determined from the actions in the textual specification, and each action is assigned to one of the pipeline stages. A shared variable is determined that is accessed by actions in at least two stages. An action in an initial stage writes the shared variable, an action in a last stage reads the shared variable. A hardware description is generated including the pipeline stages and assigned actions, a respective first-in-first-out queue between each adjacent pair of pipeline stages, a respective register for transferring the shared variable between each adjacent pair of the pipeline stages, and control logic for writing to and reading from each respective register.

Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.

Abstract: An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe endpoint device through a PCIe switch. The PCIe endpoint device is configured to initiate data transfer between the main memory and the PCIe endpoint device.

Abstract: A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.

Abstract: A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the system. A text entry pane on the display device shows a textual definition of the connection. An optional status pane shows a textual log of user-performed actions relating to construction of the system.

Abstract: Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.

Abstract: Method and apparatus for processing variable-length packets in a buffer memory for transmission are described. In some examples, as each packet of the packets is written to a buffer memory, a length of the packet is obtained from a length field therein. For each packet of the packets, the length of the packet is compared with a threshold length. An encoded length for each of the packets is stored in a sideband memory, the encoded length for each packet of the packets being: (i) the length of the packet if the length satisfies the threshold; or (ii) a predefined value if the length of the packet does not satisfy the threshold. As each packet of the packets is read from the buffer memory, an end location of the packet is determined responsive to the encoded length thereof in the sideband memory.

Abstract: Within a system comprising a processor and a memory, a method of creating a circuit design for implementation within an integrated circuit can include inserting a placeholder block into the circuit design, wherein the circuit design includes a circuit block comprising circuitry and a circuit block interface, and wherein the placeholder block is devoid of circuitry and, responsive to receiving a user input specifying a coupling between the placeholder block and the circuit block, automatically determining a plurality of attributes of the circuit block interface. The method can include automatically generating, according to the attributes and by the processor, a placeholder interface within the placeholder block, wherein the placeholder interface is complementary to the circuit block interface. The placeholder block can be stored within the memory.

Abstract: A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.

Abstract: A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the channel region of the semiconductor device. The semiconductor device further includes first and second trenches formed adjacent to the gate stack, where the first and second trenches are conically shaped to be wider at a top portion of each trench as compared to a width of each trench below the top portion of each trench. The semiconductor device further includes strained silicon alloy formed within the first and second trenches, where a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.

Abstract: Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and data signals centers the average clock edge placement. In a particular embodiment, counters, each having N bits where N is an integer, are used to count clock pulses and data bits. When one counter is full and the most-significant bit on the other counter goes high, the phase shift between the data and clock signal places the average clock edge at the data bit edge.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates.

Abstract: A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.

Abstract: A data structure and method of use thereof for encoding video information are described. Macroblock parameters are initialized, and it is determined whether an operating point is selected. If the operating point is selected, then the following occurs: each quad of nodes of a first node level are obtained and a check for merger is done on them; each quad of nodes of a second node level is obtained and a check for merger is done on them; nodes of a third node level are obtained and check for merger is done on them; nodes of a fourth node level are obtained and a check for merger is done on them; and modes are assigned responsive to cost of combinations of encoding modes associated with possible mergers.

Abstract: A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The input/output interface includes a plurality of input/output sites and an edge detector coupled to the plurality of input/output sites for detecting an edge in an input signal received by the integrated circuit. A plurality of delay lines are used to determine whether the input signal arrives too early or too late compared to a clock signal in the integrated circuit, and delays in the delay lines are adjusted to align the input signal with the clock signal in the integrated circuit.