Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: A method and apparatus is provided for the automatic creation of timing constraints that are based upon input interface timing parameters entered through a graphical user interface that is associated with the one or more input interfaces. Ideal timing constraints are created from the input interface timing parameters for the one or more input interfaces, thereby enabling the analysis of the input interface(s) without requiring explicit constraints to be defined by the designer of the input interface(s). Timing constraints may, therefore, be automatically generated by the designer without the need for the designer to possess any detailed knowledge of the associated constraint language parameters. Once created, the automatically generated timing constraints are graphically displayed to the designer for verification and/or modification. The automated process removes any potential for improperly defining the input constraint language parameters associated with the input interface(s).

Abstract: A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Abstract: An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

Abstract: An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a phase locked loop (PLL). The frequency difference is then used to adjust the local oscillator's frequency to be changed by a value that is proportional to the frequency difference measured. Through adaptive calibration of the local oscillator's frequency prior to closed loop PLL operations, a substantial reduction in the amount of time required to obtain phase/frequency coherent operation of the PLL is realized.

Abstract: Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths failing to meet the performance objective. A specification of the design is synthesized into a netlist specifying interconnections of primitive elements. The synthesis includes controlling a fanout of a primitive element on each critical timing path failing from excessive fanout. The primitive elements are placed at respective positions, including priority placement of a primitive element on each critical timing path failing from bad placement. The interconnections are routed between the primitive elements at the respective positions. The routing includes priority routing of an interconnection on each critical timing path failing from long routing. A specification of the placed and routed primitive elements is stored.

Abstract: Approaches for managing a simulation model. A processor-implemented method includes simulating an electronic system using the simulation model and a simulator. The simulation model includes an assertion test that has an associated limit. The simulator counts a number of times the assertion test is evaluated during simulation, which is the evaluation count. When the simulator determines that the evaluation count has reached the limit, the simulation is stopped.

Abstract: A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.

Abstract: Reducing peak-to-average power ratio (“PAPR”) for modulation and demodulation is described. Complex sample values are obtained in a time domain for orthogonal frequency division multiplexed (“OFDM”) signaling. The complex sample values are transformed into a frequency domain. The set of spectral samples is multiplied with a filter spectrum to shape the set of spectral samples to provide spectral products.

Abstract: A multiplier-accumulator includes a pre-adder, a multiplier, an accumulator, multiplexing logic, and control logic. The pre-adder is configured to sum a first input and a second input to produce a pre-sum output. The multiplier is configured to multiply a third input and the pre-sum output to produce a product output. The accumulator is configured to sum a pair of accumulator inputs to produce a sum output. The multiplexer is configured to select the pair of accumulator inputs from a plurality of multiplexer inputs, where the plurality of multiplexer inputs includes the product output and the sum output. The control logic is configured to control operation of the pre-adder, the accumulator, and the multiplexer logic. In an example, each of the first input, the second input, the third input, and the sum output is coupled to programmable interconnect of a programmable logic device.

Abstract: A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

Abstract: An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The rational submultiple includes an integer part and a fractional part, the fractional part including a numerator and a denominator. A dithered pulse generator is configured to produce the dithered pulse signal from a count of the reference clock signal that is reset dependent on the integer part, and a fractional phase signal from a count that is incremented by the numerator and that is reset dependent on the denominator. A phase controller is configured to delay the dithered pulse with a delay proportional to the fractional phase to produce the output clock signal. The delay may be calibrated by internal logic.

Abstract: A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.

Abstract: A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circuit design and storing power usage data, from the simulating, for each of a plurality of circuit elements of the low-level circuit design. The circuit elements can be correlated with the high-level blocks of the HLMS circuit design. A power query of a selected block of the HLMS circuit design can be received and a measure of power usage for the selected high-level block can be determined according to the power usage data for selected ones of the plurality of circuit elements correlated with the selected high-level block. The measure of power usage for the selected high-level block can be output.

Abstract: A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of CFBs of the circuit design, determining an edge weight for each edge. The CFBs can be initially placed and a distance between each pair of CFBs joined by an edge of the undirected graph can be calculated. The CFB placement can be annealed by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of CFBs joined by the edge. The cost function also can sum the products for each edge. The CFB placement can be stored.

Abstract: Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC. The method includes: obtaining design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining a layout of the TDVs in the mother IC according to the design rules; and defining at least one mask for programming interconnect on the mother IC to physically connect the TDVs between the at least one interface tile and the physical interface of the daughter IC without changing the electrical configuration of the at least one interface tile.

Abstract: Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the design block. The electronic system is simulated in the HLMS, which includes a hardware-based co-simulation platform and a software-based co-simulation platform. A hardware realization of the design block is automatically generated and the design block is emulated in the hardware based co-simulation platform using the hardware realization of the design block. A sequence of values is displayed for the selected signals of the electronic system. During the simulation of the electronic system in the HLMS, the sequence of values for the internal signals of the design block and another sequence of values for the ports of the design block are transferred between the co-simulation platforms.

Abstract: Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative description. The dependency graph specifies each rule that depends upon another one or more of the rules. The declarative description and the dependency graph are transformed into a Petri net representing the behaviors of the processor. The Petri net includes respective transitions for the rules and places for enabling the transitions to fire. A specification of the Petri net is output. The Petri net represents the behaviors of the processor.