Abstract: A computer-implemented method of verifying isolation of a plurality of instances of a redundant module of a circuit design that is implemented within a single, programmable integrated circuit can include counting component failures needed to establish a connection between at least two different ones of the plurality of instances of the redundant module. The method can include determining whether each instance of the redundant module is isolated from each other instance of the redundant module according to the counting of component failures, and outputting an indication whether each of the plurality of instances of the redundant module is isolated.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.

Abstract: Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having outputs coupled to enable inputs of the numerous DCI modules, where operating the IC in a test mode configures the control circuit to selectively couple a control signal to the enable terminals of the numerous DCI modules. One DCI module of the numerous DCI modules can be enabled at a time facilitating testing of the configurable impedances of the I/O terminals.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: Circuits detect communications from multiple transmitting antennas to multiple receiving antennas. A respective first block for each non-initial transmitting antenna determines partial distances for pairings of a first candidate and a quadrature-phase amplitude. A respective second block for the initial transmitting antenna determines partial distances for combinations of phase amplitudes. A respective second block for each non-initial transmitting antenna determines partial distances for pairings of a second candidate and an in-phase amplitude. A respective first selector for each non-initial transmitting antenna selects the first candidates from the pairings for the respective second block having smaller partial distances. A respective second selector for each non-initial transmitting antenna selects the second candidates from the pairings for the respective first block having smaller partial distances.

Abstract: A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.

Abstract: Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.

Abstract: Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.

Abstract: A computer-based system for testing a circuit design for implementation within an integrated circuit device can include a design application (205) providing simulation instructions for testing a circuit design and a simulation driver (225) receiving the simulation instructions and translating the simulation instructions into control protocol instructions specifying operations of an integrated circuit control protocol. The system can include a simulation environment (240). The simulation environment can include a communication module (245) communicating with the simulation driver, a simulation cable driver (250) receiving the control protocol instructions from the simulation driver via the communication module, and a control module (255). The simulation cable driver further can translate the control protocol instructions into signaling information corresponding to the integrated circuit control protocol.

Abstract: A method of determining a factorization permutation for a natural number can include storing a canonical prime factor vector within memory of a system and storing a first basis vector within the memory. The method can include deriving a first count sequence, including a plurality of counts, from the first basis vector, wherein each count of the first count sequence is a child of the first basis vector. For each count of the first count sequence, a second basis vector can be output that is a child of the count, wherein each count of the first count sequence and child second basis vector specifies a factorization permutation of the natural number.

Abstract: Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.

Abstract: In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.

Abstract: A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bus adapter further can be coupled to a memory map interface (135) through which at least one peripheral device communicates with the processor. Single word operations can be exchanged between the processor and the dual-bus adapter through the first communication channel. Burst transfer operations can be performed by exchanging signaling information between the processor and the dual-bus adapter over the first communication channel and exchanging data words between the processor and the dual-bus adapter through the second communication channel.

Abstract: Circuits are provided for detecting symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A circuit includes distance blocks, selectors, and an identifier block. Each distance-block includes at least one sub-block, and each sub-block inputs a candidate for a corresponding transmitting antenna. The sub-block determines partial distances for pairings of the candidate and each symbol in a constellation from a partial distance of the candidate and signals received at the receiving antennas. At least one selector assigns each pairing for each candidate for a corresponding transmitting antenna to a bin having a range that includes the partial distance of the pairing. The selector selects candidates for a successive transmitting antenna from the bins having the smaller ranges. The identifier block selects a final candidate that is one of the pairings for a last transmitting antenna having a smaller partial distance.

Abstract: A method of capturing trace data can include storing trace data from a circuit as entries within memory slots of a trace buffer. Responsive to detecting a first trigger event, a trigger bit and a time marker bit within a first trigger event entry are set, wherein the trigger bit and the time marker bit are correlated with the first trigger event. A capture region within the trace buffer having a defined range can be determined. A first time marker correlated with the time marker bit of the first trigger event entry can be stored. Content of the capture region from the trace buffer correlated time markers can be output.