Patents Assigned to Xilinx, Inc.
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Patent number: 7526689Abstract: All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.Type: GrantFiled: June 29, 2006Date of Patent: April 28, 2009Assignee: Xilinx, Inc.Inventor: Robert Yin
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Patent number: 7525331Abstract: A test circuit in an integrated circuit (200 or 300) is used for verifying a critical path of a circuit (230) under test. The test circuit can include a sequence generator (202) generating a data signal for the critical path, a source sequential circuit (208) for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (210 or 310) for receiving an output of the critical path, and an analyzer circuit (212 or 312) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin (209) or a set/reset pin (309) of the destination sequential circuit. The test circuit can further include a controller circuit (220) for strobing a comparison circuit (218) in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.Type: GrantFiled: March 6, 2008Date of Patent: April 28, 2009Assignee: XILINX, Inc.Inventors: Prabha Jairam, Himanshu J. Verma
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Patent number: 7525362Abstract: A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the circuit; and a plurality of inverters each controlled by an associated node, wherein an inverter node of each inverter of the plurality of inverters is coupled to a separate node of the predetermined nodes. A method of preventing an error in a flip-flop is also disclosed.Type: GrantFiled: March 17, 2006Date of Patent: April 28, 2009Assignee: Xilinx, Inc.Inventors: Austin H. Lesea, Tan Canh Hoang
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Patent number: 7523215Abstract: A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.Type: GrantFiled: January 14, 2002Date of Patent: April 21, 2009Assignee: Xilinx, Inc.Inventors: Moises E. Robinson, Shahriar Rokhsaz, Jinghui Lu
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Patent number: 7521987Abstract: Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.Type: GrantFiled: December 3, 2007Date of Patent: April 21, 2009Assignee: Xilinx, Inc.Inventors: Edward Cullen, John G. O'Dwyer, Jinsong Huang
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Patent number: 7521961Abstract: A system and method of configuring a partially reconfigurable switch includes a pipelined partially reconfigurable switch interconnect may include a desired subset of connections in a switch interconnect, a partial bitstream defined for each of the desired subset of connections stored in a memory such as SRAM serving as a buffer, and a controller for cyclically applying the partial bitstream to the switch interconnect. The controller may determine a connection instance and duration for each client access of the switch interconnect in a synchronous manner. A clear to send (CTS), receive data (RD), destination address, and source address at each client may be sent with each partial bitstream for each desired subset of connections. The partially reconfigurable switch and a plurality of partially reconfigurable slot clients may be formed in a silicon backplane.Type: GrantFiled: January 23, 2007Date of Patent: April 21, 2009Assignee: XILINX, Inc.Inventor: James B. Anderson
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Patent number: 7523380Abstract: A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.Type: GrantFiled: October 31, 2006Date of Patent: April 21, 2009Assignee: Xilinx, Inc.Inventor: Stephen M. Trimberger
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Patent number: 7523434Abstract: An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for proper syntax and one or more abstract syntax trees can be formed. Next, the input variables are then assigned to input ports of the dynamically configurable arithmetic unit. Then using the parsed mathematical expressions with the assigned input ports, a list of operations to be performed by the dynamically configurable arithmetic unit are determined. And lastly, an interface to the dynamically configurable arithmetic unit is generated using in part the variable-to-input port assignments and the list of operations.Type: GrantFiled: September 23, 2005Date of Patent: April 21, 2009Assignee: Xilinx, Inc.Inventors: Bradley L. Taylor, Arvind Sundararajan, Shay Ping Seng, L. James Hwang
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Patent number: 7519823Abstract: Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.Type: GrantFiled: August 12, 2004Date of Patent: April 14, 2009Assignee: XILINX, Inc.Inventors: Paul R. Schumacher, Robert D. Turney, Mark Paluszkiewicz, Prasanna Sundararajan, Brandon J. Blodget
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Patent number: 7519938Abstract: A method is provided for generating an implementation of an electronic design. Information describing a set of strategies is specified. Each strategy of the set includes one or more options for directing the generation of an implementation of the electronic design, with each option being a set of one or more input parameter values to an implementation tool. The set of strategies is displayed and a subset of the set of strategies is selected in response to user input. For each strategy of the subset, a respective implementation of the electronic design is generated from a specification of the electronic design in a hardware description language. The option or options of each strategy are input to one or more implementation tools to direct the generation of the respective implementation for the strategy. For each strategy of the subset, quality metrics are displayed for the respective implementation of the electronic design.Type: GrantFiled: October 5, 2006Date of Patent: April 14, 2009Assignee: Xilinx, Inc.Inventors: Robert E. Shortt, David A. Knol, Salil Ravindra Raje
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Patent number: 7518394Abstract: A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memory cell. The memory cell PMV may be used, for example, to measure the amount of margin available for memory cell flips and how process variation affects the memory cell write margin. The memory cell PMV is implemented as a plurality of shift register bits interconnected as a ring oscillator, where each shift register bit is comprised of a memory cell. By adjusting the drive current for each memory cell and measuring the resultant change in oscillation frequency of the ring oscillator, information may be obtained concerning process variation and its effect on memory cell performance.Type: GrantFiled: February 7, 2007Date of Patent: April 14, 2009Assignee: Xilinx, Inc.Inventors: Manoj Chirania, Philip D. Costello
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Patent number: 7518396Abstract: A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.Type: GrantFiled: June 25, 2007Date of Patent: April 14, 2009Assignee: Xilinx, Inc.Inventors: Venu M. Kondapalli, Wei Guang Lu, P. Hugo Lamarche
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Patent number: 7518401Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.Type: GrantFiled: August 29, 2006Date of Patent: April 14, 2009Assignee: Xilinx, Inc.Inventors: Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon
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Patent number: 7519747Abstract: A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.Type: GrantFiled: September 11, 2003Date of Patent: April 14, 2009Assignee: XILINX, Inc.Inventors: Warren E. Cory, Joseph Neil Kryzak
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Patent number: 7518398Abstract: An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.Type: GrantFiled: October 4, 2007Date of Patent: April 14, 2009Assignee: Xilinx, Inc.Inventors: Arifur Rahman, Stephen M. Trimberger, Bernard J. New
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Patent number: 7516437Abstract: A method of generating a low-skew network for a circuit design can include routing connections between a source and a plurality of loads of the network, determining a delay for at least one routed connection, and accepting the routed connections if the delay of each routed connection is within a skew tolerance range.Type: GrantFiled: July 20, 2006Date of Patent: April 7, 2009Assignee: XILINX, Inc.Inventors: Parivallal Kannan, Carl M. Stern
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Patent number: 7515452Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.Type: GrantFiled: January 3, 2007Date of Patent: April 7, 2009Assignee: XILINX, Inc.Inventors: Jan L. de Jong, Susan Xuan Nguyen, Raymond C. Pang
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Patent number: 7515664Abstract: Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are used with a first delay module designated as a monitor delay module to monitor the clock edge transitions, while a second delay module is designated as a data delay module that provides a data output. A controller provides for incrementing or decrementing the tap delay of both delay modules to assure clock data falls at the center of the monitoring window as determined using the monitor delay module. The controller further selects between the two delay modules as to which provides data and which is used as for clock edge monitoring when the clock edge transitions drifts to an edge of the monitoring window.Type: GrantFiled: April 21, 2005Date of Patent: April 7, 2009Assignee: XILINX, Inc.Inventor: Tze Yi Yeoh
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Patent number: 7515668Abstract: A method for correcting sampling offset of a clock and data recovery circuit begins for consecutive data bits having a transition there between by sampling, using an edge sampling point, the transition to produce a sampled transition. The method continues by determining whether the sampled transition is of an intermediate value. The method continues when the sampled transition is not of the intermediate value, by adjusting sampling position of incoming data of the clock and data recovery circuit.Type: GrantFiled: January 26, 2005Date of Patent: April 7, 2009Assignee: XILINX, Inc.Inventor: Shahriar Rokhsaz
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Patent number: 7512890Abstract: A graphical user interface (GUI) is provided with a specifiable edit control field that is accessed in conjunction with a non-edit field, the non-edit field for example being a check box, or radio buttons. The specifiable edit field can be accessed for example by right clicking or double clicking on the non-edit field or overall GUI. The specifiable edit field allows changing parameters of the non-edit field via entry of a programmatic expression that evaluates to an valid input to the non-edit field. For example in a high-level modeling program that enables modeling modules of a Field Programmable Gate Array (FPGA), when a normal editing field can modify only one module at a time, the specifiable editing field can allow modifying a plurality of modules at one time that are hierarchically linked together by the associated non-edit field, such as a check box.Type: GrantFiled: July 25, 2005Date of Patent: March 31, 2009Assignee: Xilinx, Inc.Inventors: Alexander R. Vogenthaler, Roger B. Milne