Abstract: A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Abstract: Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Abstract: Reconfiguration of a hard macro via configuration registers is described. An integrated circuit includes configuration memory cells coupled to a hard macro via configuration registers. The configuration memory cells are for storing values for initializing the hard macro. The configuration registers are coupled to be loaded with the values stored by the configuration memory cells. Write management busing is coupled to the configuration registers for overwriting at least one of the values loaded into the configuration registers for reconfiguration of the hard macro.

Abstract: A probe card configured for interchangeable heads. In one example, a probe card includes a probe card circuit board and a substrate. The substrate includes a first interface coupled to the probe card circuit board and a second interface having a plurality of die patterns. The plurality of die patterns are arranged with respect to the substrate in a plurality of probe pin configurations for a respective plurality of probe heads.

Abstract: The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data transceivers comprises a clock bus interface and a first data transceiver coupled to the clock bus interface to receive a clock signal from the clock bus interface. A clock bus coupled to receive the clock signal enables the transfer of the clock signal to an adjacent data transceiver. According to other embodiments, various clock buses and interfaces enable routing clock signals between various circuits of the integrated circuit.

Abstract: A communication circuit comprises a plurality of receivers to receive the serial data from multiple lanes of a communication channel. The receivers may convert data received from the lanes from a serial to parallel format. Decoders may identify characters recovered from the different lanes, which collectively may define a word of width (i.e., character width) related to the number of lanes. Logic may determine when at least one of a start-of-frame and an end-of-frame character has been received. Parsing circuitry may then determine valid characters of a received word based on their placement relative to a start-of-frame character and/or an end-of-frame character. A controller may control when to present recovered data to at least one of storage registers or an output port, based on the character type identified by the decoder, its placement, an amount of characters parsed, and the number of characters already stored.

Abstract: A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.

Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300 and 400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

Abstract: Method and apparatus for component naming is described. Parameters (305) for a target component are obtained (201). The parameters (305) are hashed (202) to provide a hash value (203). The hash value (203) is used to construct a name (205) of the target component.

Abstract: An entropy encoder module (350) is configured to completely perform normalization of each binary input in a single clock cycle for Context Adaptive Binary Arithmetic Coding (CABAC). Outstanding bits are separated out from other bits of a portion of a frame for Context Adaptive Binary-Arithmetic Coding (CABAC). The outstanding bits are parsed responsive to location marking, counting, and bit masking to provide insert bits. The insert bits are inserted into the encoded bitstream for output. A Context Adaptive Binary Arithmetic Coding (“CABAC”) system includes: digital information storage (301) having digital video information stored therein; and a CABAC encoder (200) coupled to the digital information storage (301) to receive a portion of the digital video information at a time.

Abstract: A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Abstract: Methods of compensating for process variations and/or mask revisions in a programmable integrated circuit (IC). A non-volatile memory in the IC stores a value representing a process corner and/or mask revision for the IC. A configuration control circuit monitors a configuration bitstream provided to the programmable IC. When no code key is received, configuration data is applied to a first (e.g., digital) circuit. When a code key is identified, the code key is compared to the stored value. If there is a match, the subsequent configuration data is applied to a second (e.g., analog) circuit. If there is no match, the subsequent configuration data is ignored until an “unlock” command is detected in the bitstream. Thus, the configuration data for the digital circuit need be included only once in the bitstream, while the configuration data for the analog circuit is supplied once for each supported process corner or mask revision.

Abstract: A method of placing a circuit design on a target device can include subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition separated by a design-cutline, and subdividing at least a portion of the target device into at least a first device-partition and a second device-partition separated by a device-cutline. The method can include determining a design-cutset corresponding to a design-cutline and calculating a measure of required wire-bandwidth for the device-cutline according to the design-cutset. The length of the design-cutline can be increased according to the measure of required wire-bandwidth, thereby altering the perimeter of the first device-partition and the perimeter of the second device-partition.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least one internal register of a hardware block in a PLD. The PLD is actively reconfigured with a first partial bitstream to sever first connections between input/output (IO) pins of the hardware block and a user design, and establish second connections between the IO pins and state access logic. The at least one internal register is accessed using the state access logic. The PLD is actively reconfigured with a second partial bitstream to establish third connections between the IO pins and the user design.