Patents Assigned to Xilinx, Inc.
  • Method and apparatus for a multiplexed address line driver
    Patent number: 7196940
    Abstract: A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory cell address line during Power On Reset (POR) to insure proper memory cell initialization during power up. Once initialized, read and write address select signals are level shifted to be equal to or greater than the read and write voltage magnitudes applied to the memory cell address line to ensure proper operation.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 27, 2007
    Assignee: Xilinx, Inc.
    Inventors: Vasisht Mantra Vadi, David P. Schultz
  • Atomic transaction processing for logic simulation
    Patent number: 7197445
    Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: March 27, 2007
    Assignee: Xilinx, Inc.
    Inventors: Kumar Deepak, Jimmy Zhenming Wang, Wei Lin
  • Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions
    Patent number: 7194705
    Abstract: Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: March 20, 2007
    Assignee: Xilinx, Inc.
    Inventors: Kumar Deepak, L. James Hwang, Singh Vinay Jitendra, Haibing Ma, Roger B. Milne, Nabeel Shirazi, Jeffrey D. Stroomer, Jimmy Zhenming Wang
  • Cost-independent critically-based target location selection for combinatorial optimization
    Patent number: 7194722
    Abstract: A method of physical design for a programmable logic device can include associating target locations for movable objects with criticality measures and calculating the criticality measure for each target location. A probability for each target location can be calculated. The probability of the target location can be dependent upon the criticality measure for that target location. The method further can include selecting a target location for one of the movable objects for controlled movement during a simulated annealing process. The target location can be selected according to the probability corresponding to each target location.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 20, 2007
    Assignee: Xilinx, Inc.
    Inventors: Salim Abid, Victor Z. Slonim
  • Method and apparatus for processing data with a programmable gate array using fixed and programmable processors
    Patent number: 7194600
    Abstract: A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: March 20, 2007
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Douglass, Ahmad R. Ansari
  • Cost-independent criticality-based move selection for simulated annealing
    Patent number: 7194721
    Abstract: A method of physical design for a programmable logic device (PLD) can include associating movable objects of the PLD with a criticality measure that is dependent upon timing information for a configuration of the PLD (115). The method further can include calculating the criticality measure for each movable object (125) and calculating a probability for each movable object (130). The probability can depend upon the criticality measure for the movable object. The method also can include selecting one or more of the movable objects for controlled move generation within a simulated annealing process (135). Movable objects are selected for controlled move generation according to the probabilities assigned to the movable objects.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: March 20, 2007
    Assignee: Xilinx, Inc.
    Inventors: Victor Z. Slonim, Salim Abid
  • Programmable logic block having lookup table with partial output signal driving carry multiplexer
    Patent number: 7193433
    Abstract: A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 20, 2007
    Assignee: Xilinx, Inc.
    Inventor: Steven P. Young
  • System and method for using a PLD identification code
    Patent number: 7191339
    Abstract: A method of programming a programmable logic device (PLD) includes identifying and reading an identification code on the PLD. At this point, a plurality of check bits can be generated based on the identification code. These check bits can be used to correct any errant bits in the identification code at a subsequent point in time. A first key is then created using the identification code. The configuration bitstream is encrypted using the first key. The encrypted bitstream and the check bits are then stored for subsequent use. To program the PLD, the stored check bits are transmitted to the PLD and used to correct any errant bits in the identification code at that point in time. A second key is then created using the corrected identification code. The encrypted configuration bitstream is then transmitted to the PLD and decrypted using the second key.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Method and apparatus for a differential driver with voltage translation
    Patent number: 7190193
    Abstract: A differential amplifier is configured to receive an input signal whose magnitude is referenced between a reference voltage and a first power supply magnitude. A differential current conducted by the differential amplifier induces current to be conducted by a first current mirror, which in turn induces current to be conducted by a second current mirror. The current conducted by the second current mirror produces an output signal that is referenced between the reference voltage and a second power supply magnitude.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventor: James P. Ross
  • Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames
    Patent number: 7191342
    Abstract: Described are methods and circuits that allow encrypted and unencrypted, or differently encrypted, configuration data to define the contents of the same physical memory frame or frames within a programmable logic device.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, William S. Carter
  • Integrated data download
    Patent number: 7191372
    Abstract: A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Successive data sets of the bitstream are sequentially processed by the test circuitry in response to the trigger signals to sequentially initialize the device's resources to various states. For some embodiments, each data set includes configuration data to configure one or more configurable elements of the device to implement a desired design and includes soft data for use by a processor embedded within the device. For one embodiment, control logic is provided to selectively wait for a predetermined time period before processing a next data set.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Neil G. Jacobson, Emigdio M. Flores, Jr., Sanjay Srivastava, Bin Dai, Sungnien Mao, Rosa M. Y. Chow, Pushpasheel Tawade
  • Dual-edge synchronized data sampler
    Patent number: 7190196
    Abstract: A dual-edge synchronized sampler having an efficient implementation for high speed and high performance operation is described. The sampler receives a data input signal and a clock input signal and uses an asynchronous level mode state machine to sample the data input signal responsive to level changes in the clock input signal. In some embodiments, the sampler includes at least one differential logic block for implementing the asynchronous level mode state machine. The sampler has symmetric clock-to-Q propagation delays for both rising and falling edges of the clock input signal. The sampler may include toggle functionality, and may include edge control logic for configuring the sampler as one of a rising edge and falling edge sampler.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventor: Alireza S. Kaviani
  • Method and apparatus for processing a circuit description for logic simulation
    Patent number: 7191412
    Abstract: Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Wei Lin, Sushama Ghanekar, Jimmy Zhenming Wang, Kumar Deepak
  • Hybrid counter with an asynchronous front end
    Patent number: 7190756
    Abstract: Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) including at least one asynchronous counter stage (341, 342, 343) having an asynchronous level-mode state machine (381, 382). The asynchronous level-mode state machine formed of Differential Cascode Voltage Switch Logic.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Alireza S. Kaviani, Carlos M. Vasquez
  • Circuit for reducing programmable logic pin counts for large scale logic
    Patent number: 7187202
    Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Queue for simplified communication within a multithreaded testbench
    Patent number: 7188041
    Abstract: A multithreaded testbench configured to verify a device under test defined by hardware description language logic can include a test case for the testbench executing within a master thread and a generator executing within a sub-thread thread of the master thread. The generator can be configured to create test vectors to be provided to the device under test. The testbench further can include one or more additional modules executing within additional sub-thread(s) of the master thread and a command queue. The additional module(s) can interact with the device under test. The command queue can be configured to store a plurality of commands registered by the master thread. The generator can obtain individual ones of the plurality of commands from the command queue for execution.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stacey Secatch
  • Integrated circuit having a lid and method of employing a lid on an integrated circuit
    Patent number: 7187077
    Abstract: The present invention relates to a lid for an integrated circuit. According to one embodiment, an integrated circuit having a lid comprises a substrate having a flat surface and extending a first length and a lid having a recess and a foot portion. The lid generally has a second length shorter than the first length, and is positioned on the flat surface of the substrate. Finally, a bonding agent is positioned on the flat surface adjacent the foot portion of the lid. According to an alternate embodiment, a second component is positioned on the substrate outside the foot portion, and an adhesive seal is positioned on the substrate adjacent the foot and covering the component. A method of securing a lid to an integrated circuit is also disclosed.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventor: Kumar Nagarajan
  • Communication signal testing with a programmable logic device
    Patent number: 7188283
    Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventors: Matthew S. Shafer, Bodhisattva Das, William C. Black, Scott A. Irwin
  • Boundary scan analysis
    Patent number: 7188043
    Abstract: A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors are used in simulation to identify circuit design characteristics for establishing a boundary scan test program. The test vectors are generated using a netlist of the circuit design. The test vectors are used to simulate operation of the circuit, and responses to the simulation are detected and used to identify design-specific circuit characteristics and a boundary scan test program is generated using the design-specific circuit characteristics.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventor: Mikhail A. Wolf
  • Programmable logic device suitable for implementation in molecular electronics
    Patent number: 7187201
    Abstract: Pullup and pulldown structures can be formed using nanoscale programmable junctions. These devices can be integrated into nanoscale circuit designs and can be programmably configured, e.g., desired resistance values set. Additionally, the pullup and pulldown devices allow for convenient integration of nanoscale devices with microscale devices.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: March 6, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger