Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A multiplexer circuits for programmable logic devices (PLDs) reduced susceptibility to single event upsets. The pass gate multiplexer circuit has N input circuits having pass gate and N memory cells controlling the pass gates. Each path between an input terminal and the output node includes two pass gates controlled by different memory cells. Therefore, a single event upset that inadvertently enables a pass gate can only short two input terminals when the other,pass gate in the affected input path is also enabled by its associated memory cell. Therefore, the multiplexer circuit with two pass gates in each input path reduces the susceptibility to single event upsets by a factor of (N−4)/N.

Abstract: A phase controller is coupled to a voltage-controlled oscillator (VCO) in a feedback configuration, thereby reducing the phase noise introduced by the VCO. As a result, circuits using the VCO, such as phase-locked loops or delay locked loops, will exhibit reduced jitter in the resulting output signals. In one embodiment, the phase controller measures successive actual periods of the VCO output clock, and in response, generates a control voltage representative of deviations in the successive actual periods of the VCO output clock. The phase controller transmits the control voltage to the VCO as a feedback control voltage. The VCO adjusts the actual period of the VCO output clock in response to the control voltage. More specifically, the VCO adjusts the actual period of the VCO output clock such that deviations in the successive actual periods of the VCO output clock are reduced.

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component (380) used for customizing the FPGA-based SoC can be configured (382) using parameters that can be automatically propagated (384) and used to configure peer system components. During configuration (388) of the peer system components, other parameters used to configure those peer system components can also be propagated (400) and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

Abstract: A narrow-band bandpass filter is implemented in a field programmable gate array (FPGA). An analog-to-digital converter quantizes an input analog signal with a high degree of precision to produce input data samples. A sigma-delta modulator re-quantizes the samples with a substantially lower degree of precision. The re-quantized samples are passed through a bandpass, lowpass, or highpass, finite impulse response (FIR) filter which operates at the lower degree of precision. The reduced degree of precision enables a substantial reduction in the number of resources required to implement the narrow-band bandpass, lowpass, or highpass filter in the FPGA. The modulator includes a predictor filter which has a center frequency coinciding with that of the FIR filter, and redistributes noise such that it is lowest within the passband of the FIR filter. The narrow-band filter design can be adapted to incorporate a single or multi-rate decimator configuration.

Abstract: A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is minimal, and is independent of the divisor. Variations include programmable divisors and multipliers and optional phase shifting.

Abstract: Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.

Abstract: Described are methods and circuits for accurately placing signal transitions, or “edges,” simultaneously on two or more pins of an integrated circuit (IC). A conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adapted to include a coincidence detector that compares the timing of edges on two input pins of the integrated circuit. The coincidence detector indicates when the two edges are coincident, allowing an operator of the tester to adjust the tester to establish coincidence. The amount of offset necessary to provide coincident edges is stored in a database for later use in deskewing edges used in subsequent tests. The integrated circuit can be a programmable logic device configured to include one or more coincidence detectors with which to place edges relative to one another on different pins.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Abstract: A self-addressing FIFO for transferring data between clock domains while avoiding the necessity of using a clock tree stores address information as bits of a data word and uses these bits to generate the next address, thus eliminating loading the clock signal with a separate counter. While data must be valid at the clock edges and the clock period still needs to be controlled, clock skew is not an issue and therefore general purpose routing may be used for the input or output clock. Users may input or output data to external devices without ever using on-board global clock resources.

Abstract: A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program (erase) voltage to prevent damage to the memory cell. The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program (erase) voltage to the memory cell without raising internal circuit nodes above the program (erase) voltage.

Abstract: A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay.

Abstract: A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system is provided. The system includes an adjustable termination resistor located on a chip and a reference termination resistor located off the chip. A bias circuit coupled to the adjustable termination resistor and the reference termination resistor causes the same current to flow through the adjustable termination resistor and the reference termination resistor. A comparator is configured to compare a first voltage drop across the adjustable termination resistor and a second voltage drop across the reference termination resistor. A control circuit is coupled to receive an output signal from the comparator. If the output signal indicates that the adjustable termination resistor has a desirable value with respect to the reference termination resistor, then the control circuit stops the calibration operation.

Abstract: An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the optical signals. Lookup tables convert optical input signals to electrical signals for selecting values in the lookup table.