Abstract: A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.

Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

Abstract: Methods and systems are provided in which logic cores from different third party core providers can be integrated for use with a single logic core generator. Core information from the various core providers is collected and formatted into a format that can be utilized by the single logic core generator. The information that is collected comprises at least one, and typically a number of different files. In some embodiments, the relevant core information is captured through the use of a graphical user interface (GUI) that guides particular core providers through a series of dialogs that capture the information. A formatting computer then takes the information and formats it into a form that can be utilized by the particular logic core generator. In the described embodiment, the information is formatted into at least one XCD file, which can then be utilized by the logic core generator. The newly-formatted cores can then be distributed to particular users for use with the core generator.

Abstract: Described are methods of adapting FIB techniques to copper metallization, and to structures that result from the application of such techniques. A method in accordance with the invention can be used to sever copper traces without damaging adjacent material or creating conductive bridges to adjacent traces. Semiconductor devices that employ copper traces typically include a protective passivation layer that protects the copper. This passivation layer is removed to render the copper traces visible to an FIB operator. The copper surface is then oxidized, as by heating the device in air, to form a copper-oxide layer on the exposed copper. With the copper-oxide layer in place, an FIB is used to mill through the copper-oxide and copper layers of a selected copper trace to sever the trace. The copper-oxide layer protects copper surfaces away from the mill site from reactive chemicals used during the milling process. In one embodiment, a copper-oxide layer of at least 40 nanometers thick affords adequate protection.

Abstract: A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: Described are programmable logic systems and methods in which programmable logic devices receive configuration data. In some embodiments, one or more input/output blocks of a programmable logic device are adapted to store a value identifying a remote memory space as a source of reconfiguration data. In other embodiments, external memory spaces for storing configuration data are adapted to store the value.

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Abstract: A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.

Abstract: A method and apparatus are disclosed for reducing the likelihood of unintentionally or irreversibly activating one or more of a programmable logic device's output elements after a programming interruption. Output disable and enable bits are moved to near the beginning and end, respectively, of a programming bitstream, thereby maximizing the amount of time the device outputs are in high impedance mode during programming, and minimizing the risk of unintentionally driving the device outputs.

Abstract: A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

Abstract: An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.

Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.

Abstract: A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.

Abstract: A high-speed, low distortion line driver that includes an amplifying circuit and a differential input amplifier. The differential input amplifier includes a 1st amplifying transistor, a 2nd amplifying transistor, a 1st controlled current source, and a 2nd controlled current source. The 1st amplifying transistor is coupled in series with the 1st controlled current source and the 2nd amplifying transistor is coupled in series with the 2nd controlled current source. The 1st and 2nd amplifying transistors are operably coupled to receive a differential input signal and provide a gained and level shifted representation of the differential input signal based on the controlled currents provided by the 1st and 2nd current sources. The amount of gain is based on the transconductance properties of the 1st and 2nd amplifying transistors and of the 1st and 2nd current sources.

Abstract: A differential comparator having offset correction and common mode control for providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.

Abstract: A multi-package module package includes a plurality of individually packaged chips. Yield is increased over conventional multi-chip packages because the individual chips can be inexpensively and fully tested before being placed into the multi-package module package. Also, the manufacturing process is simpler because the individual chips can be more easily handled while being tested and attached to the multi-package module package. Further, a standard component surface mount process is used for package assembly. Thus, no new capital investment or process development is needed.

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.

Abstract: An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.

Abstract: A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage.