Abstract: A core for a register-based programmable logic device includes a register configured to provide a hidden identifier in response to a secret unlock operation. The identifier is inaccessible during normal operation of the core implementation. The unlock operation is selected to be an action or set of actions that would typically not be performed during normal use of the core implementation. The logic associated with providing the hidden identifier in response to the unlock operation is configured to not interfere with normal operation of the core implementation. Therefore, the presence of this source identification capability is transparent to regular users (and unauthorized copyists) of the core implementation. The availability of the secondary identifier can be limited in duration to minimize the chances of accidental, or even intentional, discovery.

Abstract: A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.

Abstract: A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells.

Abstract: A method and apparatus for multilevel signaling includes processing that begins by determining multilevel signaling operation conditions. The processing then continues by generating an adjust signal based on the determined multilevel signaling operation conditions. The adjust signal is used to change the magnitude of the multilevel signals produced via the multilevel encoding. The adjust signal may vary a supply voltage and/or vary gain of an amplifier stage.

Abstract: An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: A method is provided for quickly determining low threshold voltages and high threshold voltages of a test circuit. Specifically, a transformed voltage transfer curve for the test circuit is generated. The maximum and minimum points of the transfer circuit are determined to calculate transformed voltage threshold values. The transformed voltage threshold are transformed to find the desired threshold voltages.

Abstract: An integrated-circuit using a routing ring is disclosed. The routing ring has an internal routing grid and an external routing gird. Logic circuits surrounded by the routing ring use the internal routing grid while logic circuits outside the routing ring use the external routing grid. The internal and external routing grids can use different pitches so that circuits outside the routing ring can be optimized to a first pitch. Similarly, logic circuits surrounded by the routing ring can be optimized to use a second pitch. In one embodiment, the routing ring includes a plurality of wires that connect the logic circuits surrounded by the routing ring to the logic circuits outside the routing ring.

Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.

Abstract: A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Abstract: An integrated circuit (I/C) assembly includes a dedicated voltage sensor line for determining with a high degree of accuracy the operating voltage at a predetermined sensor point on the IC die. The dedicated voltage sensor line connects the sensor point to an input/output (I/O) structure of the IC die, which in turn is connected to a voltage sense pin on the package of the IC assembly. In this manner, an end user can accurately monitor the operating voltage at the voltage sensor point on the IC. Additionally, an end user can connect a control circuit to the voltage sensor pin to control either the supply voltage or secondary parameters.

Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

Abstract: A communication device (50) operating at a plurality of frequencies has a processor (36) coupled to a semiconductor die integrated antenna structure (30) having a first integrated antenna (14) tuned to a first frequency and coupled to a first circuit (17) and at least a second integrated antenna (18) tuned to a second frequency and coupled to a second circuit (21). The processor controls either the first circuit or the second circuit or both.

Abstract: Method and apparatus for evolving an object using simulated annealing and genetic processing techniques. In various embodiments, simulated annealing and genetic processing techniques are combined to evolve a computer-represented object. In each iteration an object is mutated in proportion to a mutation level, and the mutated object is evaluated relative to satisfaction of predetermined criteria. The mutation level is reduced with each iteration as the object approaches a final solution. Poorer-performing objects are selectively mutated or discarded based on a probabilistic function. As the object approaches a final solution, the probability of keeping and mutating poorer-performing objects is reduced.

Abstract: A method for providing a core for a programmable logic device (PLD) is provided. In this method, a vendor can designate the size and ports of a core. Using this information, a user can generate a top-level design that can accommodate the core. The user can then submit that top-level design to the vendor, or a third party designated by the vendor, to generate a complete configuration bitstream for the PLD. The user can use this configuration bitstream to program the PLD, thereby implementing the top-level design including the core. The number of bits in this configuration bitstream is typically large enough to render reverse engineering economically unfeasible. Thus, the method allows vendors to retain control over their proprietary core IP and discourages undetectable use of this IP.

Abstract: A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the output pins to selected ones of the input pins and generates program code for the run-time reconfiguration program. The program code generated by the pre-route tool programs interconnect resources that make the required connections. The automatically generated program code is then parameterized and included in the run-time reconfiguration program.

Abstract: A test structure provides defect information rapidly and accurately. The test structure includes a plurality of lines provided in a parallel orientation, a decoder coupled to the plurality of lines for selecting one of the plurality of lines, and a sense amplifier coupled to the selected line. To analyze an open, a line in the test structure is coupled to the sense amplifier. A high input signal is provided to the line. To determine the resistance of the open, a plurality of reference voltages are then provided to the sense amplifier. A mathematical model of the resistance of the line based on the reference voltage provided to the sense amplifier is generated. Using this mathematical model, the test structure can quickly detect and characterize defect levels down to a few parts-per-million at minimal expense.

Abstract: Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.