Abstract: An FPGA includes a configuration control circuit having an internal memory that stores default configuration data which may configure the some or all of FPGA's logic blocks into a default state. A compressed bitstream includes one or more frame control bits indicative of whether corresponding configuration data is included in the bitstream. During configuration of the FPGA, the compressed bitstream is provided to the configuration control circuit from the external memory. As each frame control bit is received, its logic state is determined. If the frame control bit indicates that corresponding configuration data is included in the bitstream, the corresponding configuration data is read from the bitstream into a frame register. If, on the other hand, the frame control bit indicates that corresponding configuration data is not in the bitstream, default configuration data is read from the internal memory into the frame register.

Abstract: A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

Abstract: A tester to device-under-test interface is disclosed in which a PCB has a socket for a device under test (DUT), one or more cable connectors for cables from an IC tester, an interface matrix card slot having a plurality of contacts electrically connected to the DUT socket and the cable connector pins, and an interface matrix card having a plurality of horizontal and vertical conductors capable of being electrically connected to each other for mapping the proper connection of signals between the DUT socket and the tester cables.

Abstract: A typical occurrence in communication circuits, such as transmitters and receivers, is the internal transfer of a sequence of pulses, known as a clock signal, from an amplifier to a digital circuit. For proper operation, it is critical that the digital circuit accurately comprehends the clock signal. However, in some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the digital circuit to read the clock signals as having a longer or shorter duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit.

Abstract: A current source calibration circuit and methodology reduce noise generated by current switching. In one embodiment, the calibration circuit provides a random or pseudo-random clock signal to control a switching of calibration circuit. A clock signal generator has been described that provide a number of clock signals having different phases. In one embodiment, the clock signals are used to select a current source of a DAC for calibration. By using a random clock to select the current source, noise, which is generated by switching a primary current source with a backup current source, is spread out over a wider frequency range.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: A tunable differential amplifier includes an amplifier circuit, a current mirror, a dynamic current regulator, and a dynamic output common mode regulator. The current mirror is operably coupled to the amplifier circuit and controls the current flowing through each leg of the amplifier circuit. The current through the current mirror is established based on a regulated current provided by the dynamic current regulator and a common mode error current signal provided by the dynamic output common mode regulator. The common mode error signal is representative of an error between the desired output common mode of the amplifier circuit and the actual common mode of the output of the amplifier circuit. The regulated current is based on the common mode of the input of the amplifier circuit. As such, the biasing current and the common mode output of the differential amplifier is dynamically regulated.

Abstract: A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: In many electronic systems, it is common to communicate data from a transmitter in one device to a receiver in another. Accurate communications requires use of several matched clock signals. Mismatches in these clock signals cause transmitters to add “jitter” to transmitted data or receivers to be more intolerant of jitter in received signals, increasing the chances of mis-interpreting the data. Accordingly, the inventors devised an exemplary clock-distribution method which entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing one of the sets of clock signals to a set of matched components in a circuit and the other set of matched clock signals to a different set of components in the same circuit. The clock signals driving the matched components are isolated from mismatched aspects of the other components, and thus exhibit better matching.

Abstract: A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A method and structure for measuring the minimum lock frequency of a delay locked loop (DLL) within a programmable integrated circuit device such as a field programmable gate array (FPGA). The device is temporarily configured such that one DLL is programmed as a ring oscillator (RO) and connected directly to the input terminal of a second DLL (the DLL under test). Optionally, the RO is connected to the DLL under test through a divider to provide a lower DLL drive frequency. To test the DLL, the RO frequency is decreased until the DLL under test fails to lock. The frequency of the RO at that point is measured by comparing its output signal to the known frequency of an external clock source using two counters, and decremented until the DLL locks successfully. The lock frequency of the DLL under test is then computed from the ratio of the counter values.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. In a first mode, the DLL circuit counts and stores a first number of delays necessary to synchronize the two signals. In some embodiments, the circuit also stores a second value representing the number of unit delays in one clock period. In a second mode, the DLL circuit uses the first stored value to add the correct number of unit delays to the input clock signal. In some embodiments, the second stored value is used to generate phased output signals.

Abstract: The resource cost associated with each resource in a programmable logic device (PLD) can be obtained from topology information. In one embodiment, the PLD can be geometrically divided into an array of logical tiles. The cost can be set equal to the number of tiles the resource intersects (span). A signal path between a.source and a destination can be routed using this resource cost. In another embodiment, the cost is set as the maximum value between the vertical and horizontal spans (instead of the total span). This embodiment often increases the speed of routing.

Abstract: A configuration memory architecture for an FPGA eliminates the need for a regular array of word lines and bit lines. The memory includes memory bytes, each of which has eight SRAM latches, a single flip-flop and a one-of-eight decoder having data input coupled to the inverting output of the flip-flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The flip-flops of all memory bytes for a logic block are coupled together in a serpentine shift register. Loading of configuration data involves shutting down all paths through the decoder, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path on each memory byte from the output of the flip-flop to the data input of the 0 latch. The process is then repeated for the seven other SRAM latch positions.

Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop.

Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.

Abstract: A security circuit for an IEEE Standard 1149.1 compliant PLD that is controlled by a security bit or bits programmed when the PLD is incorporated into a final product. The security circuit includes a switch connected directly or indirectly into the Boundary-Scan Register (BSR) chain of the PLD. The security bit applies a control signal to the switch such that test data signals generated during INTEST procedures are either passed through the switch, or blocked by the switch. For example, when the Boundary-Scan architecture of the PLD is set for INTEST procedures when the security bit is set in a first programmed state, the logic gate passes test data from an input terminal to an output terminal. Conversely, when the security bit is set in a second programmed state, the logic gate masks the test data values received at the input terminal (i.e., the shifted test data is blocked).