Abstract: A memory system having a dual port first in, first out (FIFO) memory which performs read operations in synchronism with a read clock signal and write operations in synchronism with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. A synchronizing engine is provided to synchronize a current write address with the read clock signal, thereby creating a synchronized write address. The synchronizing engine further synchronizes a current read address with the write clock signal, thereby creating a synchronized read address. The synchronized write address is compared to the current read address to determine if a FIFO empty condition exists. Similarly, the synchronized read address is compared to the current write address to determine if a FIFO full condition exists.

Abstract: An apparatus and method for testing ball grid array integrated circuits (BGA ICs) including a nesting member resiliently supported on a contactor body via guide shafts. The nesting member includes alignment walls and an alignment plate defining chamfered through-holes. The alignment wall is slanted to provide rough alignment of the IC within the nesting member, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Spring-loaded pogo pins are mounted on a circuit board and have pointed tips extending toward a lower surface of the nesting member alignment plate. When the nesting member is pushed toward the circuit board by a device handler, the pointed tips of the pogo pins extend through the through-holes and pierce the solder balls of the IC, thereby providing electrical contact between the IC and the interface apparatus.

Abstract: A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by multiple concurrent switching events. The method is applied to CPLDs having interconnect matrices including input lines and output lines connected by programmable connection circuits, and having macrocells connected at their output to one of the input lines via first selective inversion circuits, and connected at their input to the output lines via second selective inversion circuits.

Abstract: Apparatus and methods are disclosed that provide a high bandwidth configurable tester board for use with automated testing equipment for testing integrated circuits. Power, ground and ATE signal connections are made by selected conductive pins making electrical contact between the tester board and the handler board. The tester board is configurable by physically selecting which pins make electrical connections between the tester board and the handler board.

Abstract: One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.

Abstract: An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: Non-volatile storage elements are provided in an array on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are one-time programmable devices which are programmed by rupturing their gate oxide.

Abstract: The invention provides to the user a way of ascertaining the estimated delay through a circuit, by placing a timing attribute on the schematic symbol for the circuit that automatically displays the estimated delay. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. In a first embodiment, the schematic entry software consults a macro speeds file to obtain delay information for the macro. In a second embodiment, the macro delay information is added to the standard device speeds file. In a third embodiment, the symbol file (or other file) for the macro includes a formula for the critical path delay through the macro, based on the delays in the standard device speeds file. The schematic entry software therefore uses the standard device speeds file to calculate the macro delay. According to a second aspect of the invention, schematic-entry software accepts pointer-driven (e.g.

Abstract: In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

Abstract: A method of generating and using a secure macro element for configuring programmable ICs is provided. The method provides a bitstream to a user, rather than providing a user-editable macro. Compilation software is provided to the user that combines the data from a "macro bitstream" (the bitstream comprising the macro data description) and the data from the user's own circuits to create the complete bitstream. The compilation software reserves the relevant portions of the complete bitstream for the macro, and does not assign user circuits to the areas controlled by those portions of the bitstream. In one embodiment of the invention, the user specifies a physical location on the programmable IC for the macro, so the macro data is optionally placed in a different location in the complete bitstream than in the macro bitstream.

Abstract: An interface structure for providing connections between integrated circuit (IC) devices and a device tester. The interface structure includes a printed circuit board having one or more groups of pogo pins, each group being arranged to contact the pins extending from the pin grid array package of one IC device, and includes interconnect paths from the pogo pins and the device tester. The groups of pogo pins are mounted directly into the printed circuit board in a universal footprint arrangement that is customized to receive a plurality of different pin grid array package footprints. A nonconductive cover plate is mounted over the pogo pin groups upon which the IC devices are mounted by a handler. A mother board is connected between the printed circuit board and the device tester.

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.

Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals. According to another aspect of the invention, an interconnect structure is provided that includes two multiplexers, each multiplexer receiving an input signal from a buffered output of the other multiplexer.

Abstract: Apparatus and methods are disclosed that provide a high bandwidth configurable tester board for use with automated testing equipment for testing integrated circuits. Power, ground and ATE signal connections are made by selected conductive pins making electrical contact between the tester board and the handler board. The tester board is configurable by physically selecting which pins make electrical connections between the tester board and the handler board.

Abstract: According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.

Abstract: A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines in the interconnect structure. These lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip. Access to the RAM blocks is efficient in any RAM configuration. Bidirectional buffers or pass devices segment the address and data lines at each RAM block so that a selectable number of RAM blocks can operate together as a RAM.

Abstract: A semiconductor testing system that performs real-time adjustment of programmed values for test signals using an interface between a system controller and the pin resources. The interface includes a calibration memory that contains timing offset values and amplitude level offset and gain values. An arithmetic logic unit combines these compensation values with the programmed values. The compensated values are then sent to test system registers that control pin resources, such as pin electronics of the semiconductor testing system.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

Abstract: A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin.

Abstract: In PCI devices, there are bits specified as read-only for use in configuring a system upon reset that could also be used after configuration for reading and writing. The present invention allows the use of such bit locations for other arbitrary user-defined purposes such as a mailbox register without interfering with the normal PCI local bus operation or configuration and with zero or minimum additional decode circuitry. Such user-defined registers can provide flag or mailbox type storage for various applications, and may be accessed by a configuration read/write cycle from otherwise normal memory or I/O based applications. Thus, the present invention, in effect, comprises a method for exploiting an otherwise unused storage resource in PCI or other local bus compatible devices.