Abstract: A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor.

Abstract: An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts.

Abstract: A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state indicating the connectivity state of the PIP. During a refresh cycle, each DRAM memory cell is loaded with its current logical state in order to maintain this state within the PIP. An information store contains duplicate data for each DRAM cell and this duplicate data is supplied and read during the refresh cycle in order to provide each DRAM cell with its proper logical state. In this manner, the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.

Abstract: A programmable logic array improves connectivity and more efficiently routes signals between logic blocks by allowing programmable connections between each logic block and the horizontal interconnect lines above and below the logic block. Thus, more efficient signal transfer is achieved, particularly when connectivity is required between logic blocks in adjacent rows. The logic array decreases transmission delay and frees up bandwidth on vertical interconnect lines, thereby optimizing the use of routing resources.

Abstract: A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The first transistor is coupled in series between a first voltage supply terminal and an output terminal, while the second transistor is coupled in series between a second voltage supply terminal and the output terminal. The first and second transistors share a common floating gate and a common control gate, which extends over the common floating gate. The floating gate has substantially the same layout as the control gate. When the floating gate is programmed to store charge of a first polarity, the programmable logic cell enters a non-volatile first state and provides an output signal having a first logic state. When the floating gate is programmed to store charge of a second polarity, the programmable logic cell enters a non-volatile second state and provides an output signal having a second logic state.

Abstract: A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate.

Abstract: Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described.

Abstract: A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according to the invention comprises two latches, one rising edge triggered and one falling edge triggered. One of these latches, each time the clock changes state, latches in a new value. When configured as a dual-edge flip-flop, the output of the inactive latch is fed forward to drive the output of the memory element. In one embodiment, the outputs of the two latches are multiplexed together and the clock selects the active output. According to a first embodiment of the invention, the memory element is used in an FPGA and can be programmed to function as either a latch or a dual-edge flip-flop. A second embodiment of the invention comprises a third latch. Based on the contents of a configuration memory cell, two of the three latches are selected to form a flip-flop. One such flip-flop is dual-edge, the other is single-edge.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: A programmable bidirectional interconnect circuit selectively provides either a buffered connection, a non-buffered connection, or a disconnection (tristate mode). The circuit includes six transistors coupled to a buffer and two signal lines.

Abstract: The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.

Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Abstract: Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A power-on reset (POR) circuit including a first single-level POR, a second single-level POR, a combining circuit, and a latch. Responsive to the voltage on a voltage supply terminal, the first single-level POR generates a first reset signal which terminates at a first trigger level voltage, and the second single-level POR generates a second reset signal which terminates at a second trigger level voltage. A combining circuit logically combines the first and second reset signals, and generates a combined output signal. This output signal controls a latch which provides the POR signal. When the supply voltage is below both trigger levels a POR signal is generated. When the supply voltage is above both trigger levels, no POR signal is generated. When the supply voltage is between trigger levels of the two POR circuits, the combining circuit leaves a floating output signal. Thus the latch does not switch.

Abstract: A memory cell array includes a first memory cell, a second memory cell, and a bit line which extends between the first and second memory cells. During normal operation, the bit line is used as a write path for data values to be written to the first and second memory cells. If the first memory cell is defective, the bit line is used to route the data value stored in the second memory cell to the first memory cell, effectively replacing the first memory cell with the second memory cell. In another embodiment, a memory cell array includes a first memory cell for storing a first data value and a second memory cell for storing a second data value. A first pair of bit lines are coupled to the first memory cell, and the first data value is written to the first memory cell on the first pair of bit lines. A second pair of bit lines are coupled to the second memory cell, and the second data value is written to the second memory cell on the second pair of bit lines.

Abstract: A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.