Abstract: The multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier and outputs a M+N bit product. The multiplier circuit includes a number of recoder circuits. The recoder circuits recode the N bit multiplier into fewer bits, thereby reducing the longest signal path through the multiplier circuit and increasing the speed of the circuit. In one embodiment, the recoder circuits perform a N to N/2 Booth recoding. The recoder circuits are combined with other circuitry to generate partial products. The partial products are combined in a three to two compression circuit. The compression circuit further reduces the longest signal path through the multiplier circuit. In one embodiment, the three to two compression circuits are configured in a Wallace Tree. In another embodiment, four to two compression circuits are used. The compression circuit outputs two addends. The two addends are then added in an adder to generate the product.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator RISA. Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution.

Abstract: A configuration emulation circuit generates configuration signals to emulate a programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect crossover.

Abstract: An FPGA combines antifuse and static memory cell programing technologies. Static memory cells determine the functions of the FPGA logic cells. Antifuses establish routing through the interconnect structure. Associated with each logic cell are configuration control units which store configuration information which configures the cell during normal operation. Each configuration control unit includes an SRAM memory cell. For each input terminal of a logic cell an SRAM configuration control unit selects whether an input signal is inverted or not. Other SRAM cells control whether a signal is cascaded into the logic cell from an adjacent cell, whether the cell operates as a combinational element or a latch, and whether the cell performs NOR or NAND functions.

Abstract: An interface assembly in the present invention includes a plate for mounting a test head, a plurality of alignment pins for aligning the test head to a device including a plurality of compressible pins, and a plurality of vacuum-activated components for coupling the plate to the device. After the test head is positioned in operative relation to the other device, the vacuum-activated components provide a vacuum which draws the plate and the device together. The interface assembly eliminates the purely mechanical securing of the plate to the device, thereby minimizing any rocking of the test head and ensuring equal compression of the plurality of compressible pins. The interface assembly also ensures safe user operation by providing that any obstacle (such as a user's finger) between the interface assembly and the device prevents creation of a vacuum. Thus, the present invention provides a time-efficient, reliable, safety-conscious means for positioning a test head relative to another device.

Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

Abstract: In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract: A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU.

Abstract: The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.

Abstract: Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

Abstract: A 4.times.1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell.

Abstract: A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array to implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word.

Abstract: A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip.

Abstract: A memory system and method which allows a plurality of memory circuits to be operated independently as separate memories, or jointly as a single memory. Alternatively, the selected memory circuits are operated jointly and other memory circuits are operated independently. The configuration of the memory system can be varied dynamically during operation of the memory system.

Abstract: A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration. The same pins can be used for both configuration and user logic. Also signals such as chip enable and other control signals can be modified by user logic before performing their function so that chips external to the FPGA can be eliminated. Upon power-up of the chip, each programmable switch connects its pad to the programming logic which programs configuration memory, so that the programming logic can receive instructions from an external source and control programming of the core logic of the chip. The configuration memory programs not only the internal circuitry accessed by the user but also the programmable switch itself.

Abstract: A semiconductor device tester and handler interface includes a tester mother board and a handler board. The handler board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester mother board has a central area, and first and second peripheral groupings of tester contacts fixed in location on the tester mother board. A ring of spaced electrical connectors such as compressible pogo pins on the tester mother board is positioned between the first and the second groupings of tester contacts such that the area of the handler boards available for mounting semiconductor devices is enhanced. This larger area permits testing in parallel of a plurality of semiconductor devices.

Abstract: An electrically reconfigurable multi-chip module (MCERD) comprises three electrically reconfigurable integrated circuits (ERICs) enclosed in a package. The package provides for more "extra-package" connections between the ERICs and package pins than it does "intra-package" inter-chip connections. However, configuration connections between ERICs are intra-package. The MCERD is mounted on a daughterboard which provides connections between package pins and between package pins and pins of the daughterboard. The connections between package pins define "extra-package inter-chip" connections that typically far exceed the number of intra-package inter-chip connections. The connections between package pins and daughterboard pins connect the MCERD to a host system when the daughterboard is mounted on the host system motherboard. When the MCERD and daughterboard are installed in a host system, the MCERD can be electrically configured and then operated as configured.

Abstract: A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.