Abstract: A low voltage driver circuit capable of interfacing with a high voltage node. The high voltage tolerant input/output circuit of the present invention has a first stage operating at a low voltage integrated circuit standard and a second stage capable of operating at both the low voltage and a high voltage integrated circuit standard. The second stage operates at high voltage during the tristate mode and at low voltage during an active mode. The second stage uses an output driver having a p-type pull-up transistor coupled to an input/output pad. The input/output pad interfaces with a high voltage or mixed voltage network. An isolator circuit is coupled between the first stage and the second stage for voltage isolation when the second stage is operating at high voltage. A charger circuit maintains the high voltage on a gate of the p-type pull-up transistor during the tristate mode and the low voltage during the active mode.

Abstract: A selectively decoupled latch circuit used for latching a signal. The circuit contains an input line for accepting an input signal to the circuit. A latch is connected to the input line for latching the input signal. A transfer gate is also connected to the input line and latch for transferring the input signal to the latch according to a clock signal. A transistor is connected in a series with a feedback loop associated with the latch. The transistor selectively decouples the feedback path according to the clock signal. By selectively decoupling the feedback path, it is easier for a new input signal to become latched because contention between a prior latched signal versus the new input signal is minimized. An output line is connected to the latch for outputting a latched signal.

Abstract: A two-turn programmable routing structure is provided for a programmable logic device that provides a high degree of routing flexibility, with lane-changing capability, while requiring a relatively small diffusion surface area. One routing structure according to the invention provides lane-changing capability for every interconnect line in the structure and a fast path for each interconnect line running straight through the structure. The routing structure preferably comprises a unitary elongated diffusion area separated by voltage-controlled transistor gates into serially arrayed adjacent diffusion regions. The sequential diffusion regions are connected to interconnect lines having assigned directions, and can be grouped into sets of N directions, where N is a multiple of eight. The directions associated with the set of diffusion regions follow specified rules that impart the diffusion-sharing, lane-changing, and fast-path capabilities of the routing structure of the invention.

Abstract: A selectable inverter circuit. An inverter circuit receives an input signal which is complemented before becoming an output signal. A pass-through circuit for setting the output signal equivalent to the input signal. An enabling circuit for providing power to the inverter circuit, in response to a selection signal. The enabling circuit also provides a charge storing circuit with a supplemental charge. The charge storing circuit releasing the supplemental charge to the inverter circuit, and so provides the inverter circuit with even more power. The enabling circuit activating the pass-through circuit and deactivating the inverter circuit in response to the first state of the selection signal. The enabling circuit deactivating the pass-through circuit and activating the inverter circuit in response to the second state of the selection signal.

Abstract: A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.

Abstract: An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Abstract: For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and selects which columns of memory cells are programmed. The decoder structure addresses a particular column only when an address provided by the counter matches an address in the memory cells of the decoder for that column. Bitstreams intended for older devices can be successfully loaded into newer devices. Bitstreams developed for future devices with additional features can be loaded into devices with fewer features, and the additional features are not used. The counter can be set to count not in sequential order so that if extra columns are provided, a defective column of the FPGA controlled by a corresponding column of configuration memory cells can be bypassed.

Abstract: An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.

Abstract: A carry logic circuit for a programmable logic device which uses a single function generator to create a carry propagate signal (P) and an output signal (S). The function generator includes a plurality of signal generation circuits, each of which is controlled by a first input signal (A) and a second input signal (B). One of the signal generation circuits is programmed to provide a desired carry propagate signal (P) in response to the first and second input signals (A,B). The carry propagate signal (P) is transmitted for use outside of the function generator to perform a carry propagation function for the carry logic circuit. The remaining signal generation circuits are programmed to generate one or more intermediate output signals in response to the first and second input signals (A,B). These intermediate output signals, in combination with carry propagate signal (P), are representative of the desired output signal (S).

Abstract: A structure and method are provided for designing the architecture of a routing structure in a programmable logic device that maximizes the number of possible paths for an available diffusion area. The method comprises steps for selecting wire directions for a plurality of wires interconnectible at a unitary diffusion area of an integrated circuit device or portion thereof. The steps of the inventive method result in a highly alternated array of wire directions, including serial sets of four wires composed of four wires extending in four compass directions. In one embodiment of the inventive method, the first two wire directions are repeated from set to set, while the second two wire directions are alternated. A second embodiment with a repeating pattern of 24 wire directions is also disclosed.

Abstract: A method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit. A circuit design is first captured and converted into a first representation of the circuit design. The first representation is for programming a programmable logic device. A first part of the first representation is for programming a configurable element in the programmable logic device. The first part of the first representation is used as a set of parameters for a general model of the configurable element. The second representation of the circuit includes the parameterized general model of the configurable element.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship.

Abstract: A method and apparatus for creating and utilizing a database of defective antifuses on a programmable logic device and comparing the list to a catalog of required connections in a design, wherein the process of comparing the two lists will determine whether the device, although flawed, is nonetheless compatible with the design to be implemented, thereby increasing device yield.

Abstract: A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.

Abstract: A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock.

Abstract: A programmable logic device has a configuration memory which is partitioned so that it includes at least one subarray available through the programmable interconnect of the user configurable logic to be used as user memory. Subarrays of the configuration memory have independent access logic coupled with them, and coupled to the user logic array so that they may be used independently as user memories. Subarray memory access logic is provided for each subarray of memory elements, and connected to the logic cell array, and optionally to the plurality of input/output cells on the device, including a subarray decoder used for selecting addressed memory elements in the corresponding subarray in response to address signals and control signals supplied across the interconnect structures of the logic cell array, and a subarray I/O path used to provide input and output data signals between the interconnect structures of the logic cell array and addressed memory elements in the subarray.

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A method is described for measuring localized operating temperatures and voltages on an integrated circuit. The integrated circuit includes an oscillator circuit with a frequency that varies with temperature and/or applied voltage. The frequency of the oscillator is then determined, using a constant voltage, for a number of temperatures to establish a known relationship between oscillation frequency and temperature. Once the relationship is known, a similar oscillator is included within or adjacent a second circuit of the integrated circuit. The operating temperature or operating voltage of the second circuit may then be determined by monitoring the frequency of the oscillator while the second circuit is operational.