Abstract: A plurality of DRAM cells are used to store the state of the programmable points in the FPGA ("FPGA DRAM cells"). A shadow DRAM array holds duplicate data of the plurality of DRAM cells. A DRAM cell of the shadow DRAM array is sensed during a refresh cycle. In this manner the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Abstract: A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock.

Abstract: According to the invention, a regulated voltage pump is provided which uses a chain of diodes between each of which is attached one plate of a capacitor for which the other plate is driven by a clock signal. The regulated voltage pump of the present invention uses feedback from the output signal to determine how many capacitors to pump. A comparator compares a signal related to the pumped output signal to a reference voltage (which may be the power supply voltage) and controls how many intermediate pumping capacitors receive a switching clock signal. Thus a regulated pumped voltage is provided.

Abstract: A method is described for configuring a general symbol to represent a specific symbol indicated by a user. The specific symbols are part of a library. A general symbol for which optimized implementations have been determined and stored is configured to implement the specific function specified by a user. Implementations provided for the general symbol include special functions which provide both high speed and small chip area.

Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

Abstract: A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

Abstract: A macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device. The macrocell allows a variable number of product terms to be retained by the macrocell, and a variable number of product terms to be exported to a second macrocell. The direction in which the product terms are exported can be controlled. The macrocell further allows a variable number of product terms to be received from a third macrocell and routed either to the output terminal of the first macrocell or to the second macrocell in combination with those product terms exported from the first macrocell. Methods for routing product terms using macrocells within a programmable logic device are also provided.

Abstract: The present invention provides a configurable sense amplifier for a programmable logic device (PLD) that can be turned on or off as needed. Specifically, a latch stores an enable or disable state which respectively connects or disconnects the sense amplifier to a voltage source Vcc. In this manner, the sense amplifier remains on or off until the latch is reset. In one embodiment of the present invention, a reset circuit provides a predetermined value to the latch and a pass transistor to prevent floating during a power-on operation.

Abstract: A multiplexer for a programmable logic device (PLD) includes a control line decode circuit that substantially reduces the number of control lines necessary to program a multiplexer. Each multiplexer input line is programmably connected to at least three output lines to increase the number of routing options. A TTL buffer circuit located at the output of the multiplexer provides the user with various output signal options, whereas a word line driver coupled to the TTL buffer circuit increases signal drive. Local feedback signals are provided to the multiplexer to increase PLD functionality. Signals from the I/O pads are routed directly to the multiplexer rather than the UIM, thereby improving PLD speed. Moreover, using the multiplexer minimizes the number of input lines because the UIM is still available for routing connections. Therefore, the present invention provides both fast cycle time and fast multiple level logic.

Abstract: According to the present invention, means are provided for joining metal wire segments into one or more serpentine structures during the testing phase so that a signal applied at one end will be detected at the other end if the metal segments are continuous. Metal segments connected into one serpentine chain can be simultaneously tested for continuity from a single origin and destination. Preferably two serpentine chains are provided, physically interdigitated with each other so that electrical shorts between adjacent wire segments will cause a signal applied to one serpentine chain to be detected on the other serpentine chain.

Abstract: A sense amplifier is provided that automatically determines its enabled/disabled state. The sense amplifier includes a latch to store the enable/disable signals. A global power-on-reset signal during initialization sets the state of this latch to a default configuration which disables, i.e. powers down, the sense amplifier. During configuration, an active latch enable signal forces the sense amplifier into an enable ready state. Then, a high signal is provided to each wordline associated with the bitline of the sense amplifier. This causes any erased memory cell driven by the wordlines to pull the associated bitline into a bitline low state and causes the sense amplifier output signal to switch states. This switch causes the latch to be overwritten with the opposite state, thereby enabling the sense amplifier. When the latch enable signal goes inactive after configuration of the device, the latch is set such that the sense amplifier remains enabled, i.e. powered up.

Abstract: A programmable logic device (PLD) performs a self-test erase check operation on memory elements to verify if the PLD is completely erased. The output signals of the sense amplifiers associated with the PLD bitlines drive a plurality of NMOS devices. The NMOS devices share a common source (node), thereby providing in effect an n-input NOR gate, where n is the number of bitlines in the array. The memory cells associated with an entire wordline of the PLD memory array are simultaneously checked for an erased state by bringing the wordline under test high while keeping all other wordlines low. If all of the memory cells on a wordline are erased, every sense amplifier output is low, all of the NMOS devices are off, and the output signal of the NOR gate is high due to a weak pull-up on the common node, thereby indicating that the whole column is properly erased.

Abstract: A screw shaft feed mechanism includes a screw shaft (25) rotatably supported by a frame (19) and extending in a shaft feed direction of a work table (shaft fed base) (1); a nut member (39) rotatably supported by the work table (1) and engaged with the screw shaft (25); a screw shaft drive motor (29) for rotating the screw shaft (25); and a nut drive motor (57) for rotating the nut member (39), wherein both screw shaft driving means and nut driving means are provided with a motor having a device detecting a rotational angle of a motor shaft, respectively.

Abstract: A programming system for programming an electrically programmable gate array (EPGA) provides a clocked data signal with data cycles of the form 01DD, where the 01 ensures a clock transition each data cycle and the DD constitutes two bit periods with the same data value. The timing is led by a timing sequence of the form 0100. The EPGA measures the period of the timing sequence. For each data cycle, the EPGA detects the 01 transition, then, after a delay equal to twice the measured timing sequence period, generates a clock pulse. The series of clock pulses so generated constitutes a configuration clock. The configuration clock is used to time sampling of the clocked data signal to extract a configuration data signal. The configuration clock and the configuration data signal are used in a conventional manner to program configuration EPROMs of the EPGA.

Abstract: The more highly integrated programmable circuits include several kinds of resources for implementing the user's logic diagram. The resources provided in the chip hardware are intended to implement functions commonly specified by a user. In order for a complex chip to efficiently implement a complex design, the features called for in the design must be matched with the resources offered in the chip hardware. The present invention evaluates a user's logic diagram in comparison to resources available on a particular chip and matches a plurality of features in the design to resources in the chip which can efficiently implement those features.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other of the inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.