Abstract: A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separates the metal interconnect line into a plurality of independent segments. Each of these segments can conduct signals independently from the other segments when the bidirectional buffer is in a tristate mode. Alternatively, a single signal may be routed through the entire length of the metal line in one or the other direction, and repowered along the way. One or more of the bi-directional buffers are used to actively drive the signal(s) onto later segments of the metal interconnect line.

Abstract: A sense amplifier is provided which is appropriate for reading memory cells which control N-channel transistors, and which can read single ended registers. The sense amplifier pulls bit and bitbar lines to a high voltage before reading, and interprets equal voltages on two legs as a logical 1. Several embodiments are illustrated, one of which latches the value read from a memory cell, and one of which includes two stages.

Abstract: A semiconductor device test head docking interface system includes a test head plate juxtaposed to a test head. The tester plate includes pairs of outwardly facing spaced vacuum cups and pairs of spaced guiding and locking pins between the cups. A handler plate includes pairs of vacuum cup receiving surfaces spaced to receive the vacuum cups upon a docking of the plates, and pairs of receiving sockets spaced to receive the guiding and locking pins upon a docking of the plates. Rotary actuators are mounted on the tester plate for rotating each of the guiding and locking pins in a respective one of the receiving sockets, such that engagement and a pulling vacuum in the vacuum cups against the vacuum cup receiving surfaces and rotation of the guiding and locking pins, effects docking of the tester plate and handler plate. A Z-axis adjustment is provided in each actuator.

Abstract: In accordance with the present invention, a microprocessor controlled device is provided which appears to a user to be a programmable logic device. Signals are taken from and placed on external pins in the same manner as would be done with a prior art programmable logic device. However, internal hardware which would be provided in a programmable logic device for performing the logic function is replaced by a microprocessor with associated memory. The microprocessor is programmable to read input signals from input pins, perform calculations related to the desired logic, and place signals onto output pins. Thus the function of the microprocessor controlled device as it appears from observing signals on external pins is the same as that of a prior art FPGA or other logic device.

Abstract: A system and method for event-driven simulation of a circuit is disclosed. The system includes a simulation history of events and node values at various times throughout the simulation of the circuit. The system allows the user to access the simulation history during the simulation, make changes to the state of the circuit at any time recorded within the simulation history, and resume the simulation of the circuit automatically corrected for any changes.

Abstract: A programmable logic device (PLD) for implementing pipelined designs is described. A pipeline array of registers and function generators, comprises registers and function generators arranged along a line in a first direction, the first direction being a direction of propagation of data signals, and registers and function generators arranged along a line in a second direction, the second direction being a direction of propagation of carry signals and control signals. Each of said function generators is operatively connected by routing resources to at least two of the registers within the pipeline array. A synchronization ring of the PLD comprises shift registers, each of the shift registers being programmable such that its bit length can be adjusted from one bit to a predefined maximum number of bits. The synchronization ring surrounds and is operatively connected by routing resources to the pipeline array.

Abstract: A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

Abstract: A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.

Abstract: A DRAM memory having shared read/write lines. The DRAM memory is comprised of an array of 3T memory cells. Data is digitally stored in the form of capacitors that are either charged or discharged. Horizontal data lines are used to convey data bits to be stored in the array of memory cells. Vertical read/write lines are used to perform both read and write functions. Activating a single read/write line causes a bit of data from a memory cell to be placed onto a corresponding data line. Simultaneously, an inverted copy of that data bit is stored in an adjacent memory cell. Hence, instead of having a separate read line and a separate word line for each memory cell, the present invention has a dual function read/write word line.

Abstract: A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.

Abstract: A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of periphery interconnect lines that run along the periphery of a programmable IC. Input/output blocks (IOBs) that are similarly along the periphery of the programmable IC and configurable logic blocks (CLBs) are coupled to the plurality of periphery interconnect lines using a programmable local interconnect structure. Each IOB includes an associated pad and an input/output external pin. Individual segments of the plurality of periphery interconnect lines utilize a bi-directional buffer to buffer a line of the periphery interconnect.

Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Abstract: A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.

Abstract: A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Abstract: A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase.

Abstract: A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.

Abstract: A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element.

Abstract: The direction of a bidirectional buffer inserted along a bus line is dynamically controlled to be always away from the signal source. The signals which select a tristate buffer to turn on for driving the bus also affect or determine the direction of all buffers inserted in the bus line. Since only one tristate enable signal will be active, the direction which each bidirectional buffer should drive is dynamically determined by the presently active enable signal.