Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: A circuit arrangement includes an array of MAC circuits, wherein each MAC circuit includes a cache configured for storage of a plurality of kernels. The MAC circuits are configured to receive a first set of data elements of an IFM at a first rate. The MAC circuits are configured to perform first MAC operations on the first set of the data elements and a first one of the kernels associated with a first OFM depth index during a first MAC cycle, wherein a rate of MAC cycles is faster than the first rate. The MAC circuits are configured to perform second MAC operations on the first set of the data elements and a second one of the kernels associated with a second OFM depth index during a second MAC cycle that consecutively follows the first MAC cycle.

Abstract: A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

Abstract: Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.

Abstract: A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.

Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

Abstract: Disclosed approaches for protecting against attacks on a local network device include establishing an access period associated with one remote network device of a plurality of remote network devices. The router rejects messages from remote network devices of the plurality of remote network devices not having associated access periods. The router forwards to the local network device, a message received from the one remote network device during the access period. The router rejects, in response to expiration of the access period, subsequent messages from the one remote network device to the local network device.

Abstract: Range information is determined for each variable of a circuit design. The range information is propagated from inputs to outputs of nodes of a DFG representation of the circuit design. For each multiplexer of the circuit design represented as a multiplexer node in the DFG, whether range information associated with a selector input of the multiplexer node restricts selection of data inputs of the multiplexer node to only one selected data input of the multiplexer node is determined. In response to determining that range information associated with the selector input restricts selection of data inputs to only one data input, the DFG is modified by connecting the selected data input to each load of the multiplexer node, and removing the multiplexer node, a corresponding select logic node of the multiplexer node, and nodes connected to unselected data inputs of the multiplexer node.

Abstract: Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

Abstract: Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.

Abstract: An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).

Abstract: An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.