Abstract: Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.

Abstract: Methods and apparatus are described for adding one or more features (e.g., HBM) to a qualified SSI technology programmable IC region by providing an interface (e.g., an HBM buffer region with a switch network) between the added feature device and the programmable IC region. One example IC package generally includes a package substrate; at least one interposer disposed above the package substrate; a programmable IC region disposed above the interposer; at least one fixed feature die disposed above the interposer; and an interface region disposed above the interposer and configured to couple the programmable IC region to the fixed feature die via a first set of interconnection lines routed through the interposer between a first plurality of ports of the interface region and the fixed feature die and a second set of interconnection lines routed between a second plurality of ports of the interface region and the programmable IC region.

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.

Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit configured to receive an analog input signal; a digital-to-analog converter (DAC); an adder having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit coupled to an output of the adder and configured to perform a comparison operation; and a control circuit, coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.

Abstract: A method, non-transitory computer readable medium and circuit for detecting and correcting errors in a communication channel are disclosed. The circuit includes error monitoring logic for monitoring the communication channel in real time for a performance metric, a fixed-operating point encoder/decoder coupled to the error monitoring logic for generating a bit stream containing redundant data used for the detecting and correcting, a reconfigurable controller coupled to the fixed-operating point encoder/decoder, wherein a configuration of the reconfigurable controller determines an amount of the redundant data contained in the bit stream, and a data structure implemented in a logic fabric of the circuit and coupled to the error monitoring logic, for generating the configuration of the reconfigurable controller responsive to a value of the performance metric controller.

Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.

Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Abstract: Techniques for intelligent tuning of speed models for configurable integrated circuits. The techniques consider data related to yield, quality-of-results, and data for individual programmable-interconnect-point (PIP)-contexts. More specifically, the speed of yield-related structures, quality-of-results related structures, and structures for measuring individual PIP-contexts are measured. These measurements are compared with estimated values stored as part of a speed model and scaling factors for the stored estimated values are calculated. The scaling factors are applied to the estimated values within the speed model and measurements are repeated if desired.

Abstract: Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

Abstract: Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Abstract: A method for creating a circuit design for an integrated circuit includes, responsive to a request to modify a current circuit design, determining, using a processor, a first core used in the current circuit design and predicting, using the processor, a second core not yet included in the current circuit design as a candidate core for inclusion in the current circuit design. The second core is determined based upon usage of the second core and the first core, in combination, in a plurality of example circuit designs.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.

Abstract: An integrated circuit (IC) includes a sampling circuit configured to sample a first signal based on a sampling position signal received from an eye-scan controller to generate a sequence of sampled symbols. A data checker is configured to provide an error signal including an indication of errors in the sequence of sampled symbols to the eye-scan controller. The eye-scan controller is configured to sweep from an initial position of a unit interval (UI) of the first signal to a left sweep end to generate a first sequence of sampling positions and sweep from the initial position to a right sweep end to generate a second sequence of sampling positions. The left and right sweep ends are determined based on first and second sequences of bit error rate (BERs) corresponding to the first and second sequences of sampling positions respectively.

Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

Abstract: A differential feedback equalizer is described. A differential feedback equalizer comprises a summer circuit configured to receive a differential input signal and a summer tap circuit output and to generate a summer circuit differential output; a first latch configured to receive the summer circuit differential output from the summer circuit and to generate a first differential latch output comprising a first state of the differential feedback equalizer; and a feedback circuit having a NAND gate coupled to an output of the first latch and configured to generate a differential tap feedback signal; wherein the feedback circuit comprises a NAND gate buffer that maintains the differential tap feedback signal at a predetermined voltage during a reset phase of the first latch. A method of implementing a differential feedback equalizer is also described.