Abstract: An integrated circuit (IC) is located on an IC chip and includes an integrated voltage regulator circuit that provides an internal supply voltage to the IC. A test mode signal can be received from an external pin of the IC chip. In response to the test mode signal, the IC can enter a test mode where the internal supply voltage is provided to components of the IC. Also in the test mode, voltage characteristics of the internal supply voltage are measured to produce an analog held value. The measurements occur in an analog domain and over a plurality of sample-and-hold windows. Upon completion of a measurement window, the analog held is converted to a digital value. The digital value is then stored in a memory circuit. The digital value is provided from the memory circuit to a reader device external to the IC.

Abstract: A method, computer system, and computer-readable medium for determining a first decoupling constant for circuitry. The method includes determining a target impedance value and a first step current value for the circuitry. The method also includes iteratively simulating a model of the circuitry while adjusting a first number of first decoupling capacitors until impedance across a range of frequencies is below the target impedance value to obtain a first final number of first decoupling capacitors. The method further includes calculating a first decoupling constant based on the first step current value and the first final number of first decoupling capacitors.

Abstract: Data exchange between a memory mapped interface and a streaming interface may include receiving sub-packets of a packet from a first interface, storing the sub-packets within a memory at addresses determined according to a ratio of a width of the first interface and a width of a second interface, and determining occupancy, of the memory as the sub-packets are stored. Responsive to determining that the occupancy of the memory meets a trigger level, sub-packets may be read from the memory at addresses determined according to the ratio and sending the sub-packets using the second interface.

Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.

Abstract: A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.

Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

Abstract: An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

Abstract: Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband.

Abstract: Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.

Abstract: A system includes an integrated circuit coupled to the memory. The integrated circuit is configured to receive first and second complex numbers at one or more data inputs. A first value is determined using a first set of product arrays of a first real number multiplier. A second value is determined using a second set of product arrays of the first real number multiplier and a third set of product arrays of a second real number multiplier. A third value is determined using a fourth set of product arrays of the second real number multiplier. A real value of a first product of the first complex number times a second complex number is determined using the first value and the second value. An imaginary value of the first product is determined using the second value and the third value.

Abstract: A system includes global memory circuitry configured to store input tensors and output tensors. Row data paths are each connected to an output port of the memory circuitry. Column data paths are connected to an input port of the memory circuitry. Processing elements are arranged in rows and columns along the row data paths and column data paths, respectively. The processing elements include local memory circuitry configured to store multiple masks and processing circuitry. The processing circuitry is configured to receive portions of the input tensors from one of the row data paths; receive masks from the local memory circuitry; perform multiple tensor operations on a same received portion of an input tensors by applying a different retrieved mask for each tensor operation; and generate, using results of the multiple tensor operations, an output for a corresponding column data path.

Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

Abstract: A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data included within each packet generated by the packetizer block.

Abstract: Methods and apparatus are described for pinning out multiple memory devices using shared conductors therebetween and providing multiple chip select signals to indicate to which of the memory devices address signals on the shared conductors apply. In the case of a clamshell configuration with a top memory device having a corresponding bottom memory device and shared vias coupled therebetween, sharing two address signals for each shared via in this manner reduces the total number of vias used, thereby reducing routing congestion and enabling the addition of ground vias around the shared vias to reduce crosstalk for the address signals.

Abstract: A processing subsystem for providing diagnostic of a processing system is provided. The processing subsystem includes a real-time processing unit that receives a first input that includes data from one or more sensors and processes the first input to generate first output that controls an actuator. The processing subsystem also includes a power and safety management unit that receives a second input and processes the second input to generate second output for testing of the first output. A method and a system for providing diagnostic for a processing system are provided as well.

Abstract: A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the processor, the second look-up table structure and routing, using the processor, the second look-up table structure.

Abstract: Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.