Patents Assigned to Xilinx, Inc.
  • Patent number: 9755600
    Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventors: Didem Z. Turker Melek, Parag Upadhyaya, Kun-Yung Chang
  • Patent number: 9755649
    Abstract: A method for protecting an integrated circuit device against security violations includes monitoring a component of the integrated circuit device for security violations. A security violation of the component of the integrated circuit device is then identified. The component of the integrated circuit device is then internally destroyed in response to the identified security violation by providing current to the component beyond a tolerable limit of the component.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventors: Richa Singhal, Edmond Jordan, Ahmad R. Ansari
  • Patent number: 9756154
    Abstract: A system for processing data includes a filtering module having a plurality of processing units, a state accumulator, and a merging network coupled to the processing units and the state accumulator. Each processing unit is configured to output a set of two sub-state vectors and a packet continuance indicator. The state accumulator is configured to store a state resulted from previous processing cycles by the processing units. The merging network is configured to output a master state vector based at least in part on the set of two sub-state vectors, the stored state, and the packet continuance indicators output from the processing units.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventor: Weirong Jiang
  • Patent number: 9755655
    Abstract: Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature (“PVT”) and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering the voltage supply to the reset devices. The input referred RMS noise and offset voltage of the circuit can be improved (reduced) by raising the voltage supply to the reset devices. Similarly, increases in Vcm due to process and voltage scaling can be mitigated by raising the voltage supply to the reset devices. Control systems are also provided herein to control the voltage supply to the reset devices to accomplish these and other objectives.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventor: James G. Hudner
  • Patent number: 9755792
    Abstract: An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence (“QPRBS”). In an apparatus, there is a pseudo random binary sequence (“PRBS”) generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is configured to receive the mask output and the PRBS to bitwise mask the PRBS with the mask output to generate the QPRBS.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventor: Winson Lin
  • Patent number: 9746864
    Abstract: An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor. The voltage regulator further includes an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 29, 2017
    Assignee: XILINX, INC.
    Inventors: Nakul Narang, Kee Hian Tan
  • Publication number: 20170244371
    Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Applicant: Xilinx, Inc.
    Inventors: Didem Z. Turker Melek, Parag Upadhyaya, Kun-Yung Chang
  • Patent number: 9742597
    Abstract: An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 22, 2017
    Assignee: XILINX, INC.
    Inventors: Kun-Yung Chang, Siok Wei Lim, Kee Hian Tan
  • Patent number: 9742380
    Abstract: An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 22, 2017
    Assignee: XILINX, INC.
    Inventors: Mayank Raj, Parag Upadhyaya, Adebabay M. Bekele
  • Publication number: 20170236809
    Abstract: A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.
    Type: Application
    Filed: February 16, 2016
    Publication date: August 17, 2017
    Applicant: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Mohsen H. Mardi, David M. Mahoney
  • Patent number: 9734032
    Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system is configured to operate a hardware portion of the user design. The processing sub-system configured to execute a software portion of the user design. The safety sub-system is configured to perform a set of operations to detect errors in the programmable IC. The first set of operations writes to at least one of a set of registers using a write macro function. In response to writing to the register with the write macro function, a list of registers stored in the memory is updated to include the register. Registers included in the list of registers are tested to determine whether or not an upset has occurred.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 15, 2017
    Assignee: XILINX, INC.
    Inventor: Sagheer Ahmad
  • Patent number: 9729153
    Abstract: A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Benjamin S. Devlin
  • Patent number: 9729170
    Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventors: Arianne B. Roldan, Hsung Jai Im
  • Patent number: 9727416
    Abstract: An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventor: Christopher H. Dick
  • Publication number: 20170220508
    Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Applicant: Xilinx, Inc.
    Inventors: Alireza S. Kaviani, Pongstorn Maidee, Eric F. Dellinger
  • Publication number: 20170220509
    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Applicant: Xilinx, Inc.
    Inventors: Alireza S. Kaviani, Pongstorn Maidee, Ivo Bolsens
  • Patent number: 9720868
    Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: August 1, 2017
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Sarosh I. Azad
  • Patent number: 9721649
    Abstract: A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 1, 2017
    Assignee: XILINX, INC.
    Inventors: Shidong Zhou, Jing Jing Chen
  • Patent number: 9721528
    Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic data to the programmable logic.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 1, 2017
    Assignee: XILINX, INC.
    Inventor: Ygal Arbel
  • Patent number: 9722604
    Abstract: In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 1, 2017
    Assignee: XILINX, INC.
    Inventor: Junho Cho