Abstract: A system includes an integrated circuit (IC) chip with connections to plurality of external pins. An integrated voltage regulator circuit is configured to provide an internal supply voltage to the IC chip. Isolation circuitry is configured to inhibit tampering of the internal supply voltage through the external pins. An analog to digital converter (ADC) circuit is configured to monitor parameters of the internal supply voltage. Security circuitry is configured to detect, using the monitored parameters, indications of tampering and to generate an error signal in response to detecting an indication of tampering.

Abstract: A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.

Abstract: An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. A mask is coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output. A synthesis filter bank is coupled to the mask. The synthesis filter bank is configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth. The second bandwidth is different than the first bandwidth for the variable bandwidth filtering.

Abstract: Systems, and related methods, relating generally to electro-absorption modulation are described. In a system therefor, there is a waveguide. A photodetector is configured with respect to the waveguide for detecting luminous intensity of an optical signal. An electro-absorption modulator is configured with respect to the waveguide for electro-absorption modulation of the optical signal. An integrated heating element is located alongside and spaced apart from both the photodetector and the electro-absorption modulator. the integrated heating element is configured for controllably heating the photodetector and the electro-absorption modulator.

Abstract: Using a storage interface circuit of a programmable IC, a first set of configuration data can be communicated between a storage circuit and the programmable IC. Using the first set of configuration data, the programmable IC can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module and programmable logic of the programmable IC. Using direct memory access (DMA) transfers through the bus interface module, a second set of configuration data can be communicated between a memory circuit and the programmable IC. Using the second set of configuration data, the programmable logic of the programmable IC can be programmed.

Abstract: Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the edges that includes a maximum number of disjoint edges is determined. Pairs of signals represented by the respective vertices connected by the edge are routed over a respective one of the channels. For vertices not connected to an edge in the subset, the signals represented by the vertices are routed via a respective one of the channels.

Abstract: A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.

Abstract: An example method of exchanging data between a remote host and a target system includes receiving at least one remote descriptor from the remote host over a front-end fabric at a controller, the at least one remote descriptor specifying a remote buffer in a remote memory of the remote host that is larger than a page size. The method includes adding entries to a table that map the remote buffer to a plurality of page-sized virtual buffers in a virtual address space managed by the controller, generating local descriptors referencing the plurality of paged-sized virtual buffers, receiving a sequence of page-sized direct memory access (DMA) requests at the controller, generating a sequence remote DMA (RDMA) requests from the sequence of DMA requests based on the entries in the table, and sending the sequence of RDMA requests to the remote host over the front-end fabric.

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Abstract: A method of enabling a communication channel between a first communication circuit and a second communication circuit is described. The method comprises establishing a communication link according to a communication protocol between the first communication circuit and the second communication circuit, wherein the communication protocol enables the transmission of data between the first communication circuit and the second communication circuit at a standardized data rate; determining a standardized data rate for which the communication link between the first communication circuit and the second communication circuit fails to meet a predetermined quality threshold; and establishing a communication link according to the communication protocol at a non-standardized data rate below the determined standardized data rate.

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

Abstract: An example semiconductor device includes a first integrated circuit (IC) die including a first column of cascade-coupled resource blocks; a second IC die including a second column of cascade-coupled resource blocks, where an active side of the second IC die is mounted to an active side of the first IC die; and a plurality of electrical connections between the active side of the first IC and the active side of the second IC, the plurality of electrical connections including at least one electrical connection between the first column of cascade-coupled resource blocks and the second column of cascade-coupled resource blocks.

Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

Abstract: A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first device disposed in a first portion of the interconnect structure. A first shielding plane including a first conductive material is disposed in a second portion of the interconnect structure over the first portion of the interconnect structure. A second device is disposed in a third portion of the interconnect structure over the second portion of the interconnect structure. An isolation wall including a second conductive material is disposed in the first, second, and third portions of the interconnect structure. The isolation wall is coupled to the first shielding plane, and surrounds the first device, the first shielding plane, and the second device.

Abstract: An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

Abstract: A method for fabricating an interposer wafer includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.