Abstract: A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further comprises a non-transitory medium for storing the encoding parity-check matrix, wherein the non-transitory medium is a part of the encoder or is communicatively coupled to the encoder.

Abstract: An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks implemented in the programmable logic. The method further includes obtaining a parameter set from the characterization database based on the description of the performance objectives. The method further includes generating a parameter image for setting registers of the processing system based on the parameter set.

Abstract: A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.

Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract: In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period.

Abstract: A phase interpolator includes: a digital-to-analog converter to generate bias signals associated with phase signals; a multiplexer having an input interface and an output interface, wherein the digital-to-analog converter is coupled to the input interface of the multiplexer; a first current source; and a second current source; wherein the digital-to-analog converter is configured to provide bleeder current signals to the first current source and the second current source while bypassing the multiplexer.

Abstract: Buffer rate control generally relates to outputting data at either a first rate or a second rate responsive to a fill level of the buffer. In an apparatus therefore, there is a buffer for receiving a data-signal input and for providing a data-signal output. A controller is coupled to receive fill-level information from the buffer and coupled to provide rate-control information to the buffer. The rate-control information is for controlling an output rate of the buffer for the data-signal output to be provided to a bus. The output rate is either a first rate or a second rate for providing the output rate of the data-signal output to the bus. The fill-level information is for selecting either the first rate or the second rate responsive to the buffer being either above or below a threshold fill level, respectively.

Abstract: Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second startup instruction causes the first processor to send a further instruction to a second processor of the device to perform a second task. At least a portion of the first task and at least a portion of the second task are performed at a same time.

Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.

Abstract: In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer.

Abstract: Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

Abstract: Circuits and methods for power dependent selection of boot images are disclosed. In an example implementation, an apparatus includes a memory circuit and a processor disposed on an integrated circuit die. The processor is configured to retrieve and execute instructions from the memory circuit. The apparatus also includes a power management circuit configured to determine a value indicative of an amount of power available to power the IC die. A boot loader circuit is coupled to the power management circuit and is configured to select one of a plurality of boot images based on the determined value indicative of the amount of power available. The boot loader circuit loads a set of instructions included in the selected one of the boot images into the memory circuit and enables the processor to execute the set of instructions.

Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

Abstract: Simulators are linked to a circuit design tool by establishing a plurality of simulator objects in response to a plurality of registration commands, respectively. Each registration command specifies a simulation interface application associated with one of the simulators, and the simulation interface application has procedures for initiating functions of the associated simulator. For each simulator, values of properties of the simulator are stored in the respective simulator object. The values of the properties include references to the procedures of the associated simulation interface application. An interface, which is responsive to input commands, accesses the values of the properties and executes the procedures referenced by the values of the properties to initiate the functions of the simulators.

Abstract: Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.

Abstract: An integrated circuit (IC) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the IC. Using the bus interface module, a second boot image is received from the memory of the host device to a memory of the IC. The IC is booted by executing the second boot image.

Abstract: An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.