Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.

Abstract: A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG).

Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

Abstract: An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.

Abstract: A TSV interposer having a reinforced edge and methods for fabricating an IC package utilizing the same are provided. In one embodiment, a chip package includes an interposer having a wiring layer and a die disposed on a surface of the interposer. The die is electrically connected to the wiring layer of the interposer. A die underfill material is disposed between the interposer and the die. The die underfill material at least partially covers a side of the die that extends away from the surface of the interposer. Stiffening material is disposed in contact with the interposer and the die underfill material.

Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

Abstract: Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the transaction. For each line representing a transaction, the start end of the line is located at a first x-coordinate corresponding to a start time of the transaction and a first y-coordinate of zero. For each line, the terminating end of the line is located at a second x-coordinate corresponding to an end time of the transaction and a second non-zero y-coordinate that is the same for each line. Each line is displayed on the display device using the processor in combination with the x-y coordinate system.

Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

Abstract: An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow graph. The nodes include a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.

Abstract: Using a storage interface circuit of a programmable IC, a first set of configuration data can be communicated between a storage circuit and the programmable IC. Using the first set of configuration data, the programmable IC can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module and programmable logic of the programmable IC. Using direct memory access (DMA) transfers through the bus interface module, a second set of configuration data can be communicated between a memory circuit and the programmable IC. Using the second set of configuration data, the programmable logic of the programmable IC can be programmed.

Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

Abstract: An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses.

Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

Abstract: Circuits and approaches for de-initializing memory circuits. In one implementation, a memory circuit includes a plurality of memory cells. Each memory cell includes a pair of cross-coupled inverters and first and second access transistors coupled to the pair of cross-coupled inverters. A first bit line is coupled to the first access transistor, and a second bit line is coupled to the second access transistor. A de-initialization circuit is coupled to the first and second bit lines. The de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a de-initialization signal.

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

Abstract: An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.