Abstract: An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

Abstract: Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

Abstract: In an example implementation, a method of implementing a circuit design for an integrated circuit (IC), includes: on at least one programmed processor, performing operations including: processing a description of the circuit design having logic elements into a graph having nodes representing the logic elements and edges representing potential pairs of the logic elements; determining a packing of pairs of the nodes to divide the graph into selected nodes and unselected nodes and selected edges and unselected edges by performing iterations of: identifying an augmenting path in the graph between a pair of unselected nodes; and modifying the selected nodes and unselected nodes and the selected edges and unselected edges based on the augmenting path; and grouping the logic elements in the description into pairs of logic elements based on the packing of pairs of the nodes.

Abstract: A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Abstract: A circuit for generating a digital image is described. The circuit comprises an image capture circuit; an edge mapping circuit coupled to the image capture circuit, the edge mapping circuit generating a mapping of edges in the image; and an edge enhancement circuit coupled to the edge mapping circuit. The edge enhancement circuit modifies aberrations in the image which are associated with an edge based upon a coefficient of a plurality of directional coefficients associated with an edge. A method of generating a digital image is also described.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: A semiconductor package with thermal neutron shielding is disclosed. The semiconductor package includes a substrate and an integrated circuit die disposed on the substrate. The semiconductor package also has a thermal neutron shield including a shielding material. The shielding material includes boron-10 and is configured to inhibit a portion of thermal neutrons that encounter the thermal neutron shield from passing through the thermal neutron shield.

Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

Abstract: In an approach for processing a circuit design by a programmed processor, a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC) is input. A critical path is determined from a first sequential element to a second sequential element assigned to the placed circuit design. A first clock buffer that provides a clock signal to the first and second sequential elements is determined, and an unused clock buffer is selected based on proximity to the first sequential element. The circuit design is modified to include the unused clock buffer as a second clock buffer coupled to receive a clock signal in parallel with the first clock buffer and to provide a clock signal to the first sequential element.

Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Abstract: An apparatus includes a first programmable circuit block including a plurality of programmable circuit elements. The plurality of programmable circuit elements include a hardwired, instrumented memory element. The instrumented memory element includes a first flip-flop configured to receive a data signal, a delay circuit configured to generate a delayed version of the data signal, and a second flip-flop identical to the first flip-flop and configured to receive the delayed version of the data signal. The instrumented memory element also may include a comparator configured to compare an output signal from the first flip-flop and an output signal from the second flip-flop and an error signal generator. The error signal generator is configured to generate an error signal responsive to a mismatch of bits between the output signal from the first flip-flop and the output signal from the second flip-flop.

Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract: A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Abstract: Various example implementations are directed to circuits and methods for debugging multiple integrated circuit (IC) packages. According to an example implementation, a first logic analyzer in a first IC package determines a latency of a data link. In response to test input data, the first logic analyzer communicates the test input data to a second IC package, via the data link, and captures a first set of data signals from a logic circuit in the first IC package. In response to test input data, a second logic analyzer in the second IC package captures a second set of data signals from a second logic circuit and communicates the second set of data signals to the first logic analyzer circuit via the data link. The first logic analyzer aligns the first and second sets of data signals, based on the determined latency, and outputs the aligned sets of data signals.

Abstract: Approaches for using a physically unclonable function (PUF) as a key-encrypting key are disclosed. Data is encrypted using a session key, and at least one PUF value is generated from a PUF. The session key and a correctness indicator are encrypted into a corresponding session key pair using the PUF value. Each session key pair is added to the encrypted data. Subsequent decryption, using a subsequently generated PUF value, of the correctness indicator to an expected value indicates a valid decryption. Decryption may be repeated using a different PUF value if the correctness indicator does not match the expected value. In another approach, the session key may be omitted and the payload data may be encrypted with the different PUF values and paired with correctness indicators.

Abstract: An integrated circuit includes an interposer die having a surface, a first die mechanically and electrically attached to the surface of the interposer die, and a second die only mechanically attached to the surface of the interposer die using a die attach adhesive.

Abstract: A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.