Patents Assigned to Zarlink Semiconductor Inc.
  • Publication number: 20030177156
    Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.
    Type: Application
    Filed: January 21, 2003
    Publication date: September 18, 2003
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
  • Publication number: 20030169841
    Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
    Type: Application
    Filed: January 31, 2003
    Publication date: September 11, 2003
    Applicant: Zarlink Semiconductor Inc.
    Inventor: Robertus Laurentius van der Valk
  • Publication number: 20030155950
    Abstract: A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.
    Type: Application
    Filed: December 27, 2002
    Publication date: August 21, 2003
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius van der Valk, Gerrit Dijkstra, Philip Ching
  • Patent number: 6608897
    Abstract: A method of canceling echo signals in a telephone network operating in a double talk mode has been developed. A system for implementing the method is also presented. In the invention the conventional normalized least mean square (NLMS) algorithm for echo cancellers is modified such that echo path changes continue to be tracked even after a double talk condition has been detected. The modified algorithm, known herein as a double-talk normalized least mean square (DNLMS) algorithm adaptively adjusts the convergence rate based on the power difference between the echo signal or the residual signal and the far end signal.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: August 19, 2003
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Gary Q. Jin, Gordon J. Reesor, Thomas Qian
  • Patent number: 6603759
    Abstract: A system is provided for carrying synchronous voice payloads of variable size across a packet-based network while eliminating network jitter losses. According to the preferred embodiment, two concurrent tasks are implemented. A Voice Packet Processing task receives packetized voice from a packet oriented interface, processes headers of the packet, and builds a receive payload buffer that is managed by means of copying packets to the synchronous interface according to the contents of the payload buffer. The Voice Packet Forwarding task builds a transmit payload buffer for voice samples received from the synchronous interface, builds the necessary protocol headers and forwards the packet to the packet oriented interface.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: August 5, 2003
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Andre Moskal, Andre Diorio
  • Publication number: 20030137329
    Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 24, 2003
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
  • Patent number: 6590974
    Abstract: A digital signal processing algorithm to cancel howling in a telephone circuit, the telephone circuit being characterized by a receive path and a transmit path in an effective closed loop configuration. The algorithm monitors input samples taken from the receive path and, if a howling signal is detected, controlled amounts of attenuation are introduced to the loop until howling is cancelled. In a preferred embodiment a prediction logic is included in the algorithm to verify the howling signal.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: July 8, 2003
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Corneliu R. Remes
  • Patent number: 6578105
    Abstract: Data is written into a circular buffer at an address pointed to by a write pointer. A number is written into the address with the data. Each time the circular buffer is traversed by the write pointer this number increments modulo a predetermined number. This number makes the circular buffer appear longer than it really is and can be used to identify underruns. The buffer has application in a segmentation and reassembly device for ATM constant bit rate services.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: June 10, 2003
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Dawn Finn, George Jeffrey
  • Patent number: 6522747
    Abstract: In a method of processing an input signal, the input signal is divided into a plurality of subbands with the aid of bank of complex valued, single-sided subband filters. The single-sided frequency spectra of the resulting subbands make aliasing negligible at near twice the critical downsampling rates.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: February 18, 2003
    Assignee: Zarlink Semiconductor Inc.
    Inventors: James Reilly, Nima Ahmadvad, Mike Seibert, Gordon Reesor
  • Patent number: 6480047
    Abstract: A digital phase locked loop (PLL) for recovering a stable clock signal from at least one input signal subject to jitter. The PLL has a digital controlled oscillator for generating a desired output and a stable local oscillator or providing clock signals. A plurality of hierarchical, multi-stage delay lines are provided to generate the required output frequencies for stable T1, E1 and ST3/OC3 timing references.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: November 12, 2002
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Hazem Abdel-Maguid, Simon J. Skierszkan
  • Publication number: 20020090080
    Abstract: A system and a method are described for detecting the line status (on-hook/off-hook) of a telephone terminal connected in parallel with a second communications terminal at a customer premises using a loop voltage detection circuit. The telephone terminal and second communications terminal being connected to the Public Switched Telephone Network (PSTN). The system detects a transition on Tip with respect to Ring on a telecommunications transmission line and ensures that the transition is of sufficient duration before providing an output. The system will ignore glitches, transient open circuits, TIP/RING polarity reversal, TIP ground and/or RING ground and Ringing. The system will detect line status for positive or negative TIP/RING polarity.
    Type: Application
    Filed: November 26, 2001
    Publication date: July 11, 2002
    Applicant: Zarlink Semiconductor Inc.
    Inventor: Paul Michael Tiernan
  • Patent number: 6408275
    Abstract: A method of compressing audio data comprising the steps of receiving a stream of digital audio samples; masking a predetermined number of lower order bits from each one of the samples; and shifting an identical number of higher order bits from an adjacent one of the digital audio samples into the respective samples so as to occupy bit locations of the lower order bits which have been masked.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: June 18, 2002
    Assignee: Zarlink Semiconductor, Inc.
    Inventor: Roger Bastin
  • Patent number: 6404888
    Abstract: A confusion data generator for the generation of non-linear confusion data utilizes a plurality of arrays acting as non-linear state machines to generate a stream of confusion data of a certain width. Each non-linear state machine contributes equally to the overall width of the confusion data. The output bit stream from the confusion data generator is then used with a combiner such as an XOR combiner to generate secure text from plaintext. The confusion data generator can be used to securely store data on a storage medium or transmit data over a communication medium. The confusion data generator is computationally inexpensive, scalable and provides good security when used with a combiner, such as an XOR combiner, to generate secure text.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: June 11, 2002
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Abdulkader Omar Barbir
  • Patent number: 6393125
    Abstract: A method and apparatus for the initialization of a class of non-linear confusion data generators is especially useful to enhance the security of non-linear confusion data generators that are restricted to short size secret keys or seeds. The initializer utilizes a user seed and a displacement distance to single or multiple secret key and cipher arrays to randomize confusion data generators such that their security is enhanced. The initializer provides the ability to design confusion data generators that are capable of securing large size data files as a collection of smaller size segments that can be independently decrypted for fast access and review. The initializer can be used to securely store data on a storage medium or transmit data over a communication medium.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: May 21, 2002
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Abdulkader Omar Barbir
  • Patent number: 6372671
    Abstract: A dielectric layer of silica glass is formed by plasma enhanced chemical vapor deposition (PECVD) wherein a gaseous precursor of the dielectric layer is supplied to a deposition chamber in the presence of an electromagnetic field. The supply of the gaseous precursor is discontinued while continuing to maintain the electromagnetic field for a delay time exceeding 0.5 seconds after the discontinuation of the supply of the gaseous precursor. This improves the hydrophilic properties of said film. A siloxane-based SOG film is deposited on the dielectric layer.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 16, 2002
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Vincent Fortin