Patents Assigned to Zarlink Semiconductor Inc.
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Publication number: 20040264478Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.Type: ApplicationFiled: February 18, 2004Publication date: December 30, 2004Applicant: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Willem L. Repko
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Patent number: 6826149Abstract: A cell transmission rate controller for use in providing constant bit rate services in an ATM or like network has a predictor for determining the payload size of the next cell, and a plurality of buffers for storing TDM data. A control circuit monitors the buffers and generates a trigger signal to produce a cell when sufficient TDM data has accumulated to fill the next cell.Type: GrantFiled: October 20, 2000Date of Patent: November 30, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Stephen Routliffe
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Patent number: 6825127Abstract: In a method of fabricating a microstructure for micro-fluidics applications, a mechanically stable support layer is formed over a layer of etchable material. An anisotropic etch is preformed through a mask to form a pattern of holes extending through the support layer into said etchable material. An isotropic etch is performed through each said hole to form a corresponding cavity in the etchable material under each hole and extending under the support layer. A further layer of depositable material is formed over the support layer until portions of the depositable layer overhanging each said hole meet and thereby close the cavity formed under each hole. The invention permits the formation of micro-channels and filters of varying configuration.Type: GrantFiled: July 24, 2001Date of Patent: November 30, 2004Assignee: Zarlink Semiconductor Inc.Inventors: Luc Ouellet, Heather Tyler
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Publication number: 20040223518Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.Type: ApplicationFiled: February 18, 2004Publication date: November 11, 2004Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Willem L. Repko, Robertus Laurentius Van Der Valk, Petrus W. Simons
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Patent number: 6813350Abstract: An apparatus for detecting a dual tone alert signal in a telephone system capable of at least off hook mode operation includes a processing channel for each tone. Each channel consists of a bandsplit filter for extracting the tone of interest and attenuating the other tone; a comparator for comparing the output of said bandsplit filter with a threshold value; and an adaptive threshold generator for generating said threshold value adapted to the amplitude of the output of said bandsplit filter to reject speech and music imitations. The apparatus offers improved talkdown and talkoff immunity.Type: GrantFiled: December 5, 2000Date of Patent: November 2, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Philip Ching
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Patent number: 6795520Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.Type: GrantFiled: January 31, 2003Date of Patent: September 21, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Robertus Laurentius Van Der Valk
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Patent number: 6795514Abstract: A circuit for extracting a data clock signal from an input data stream, comprising a programmable delay element for receiving an arbitrary clock signal, delaying the arbitrary clock signal by a variable programmable amount and in response generating an extracted data clock signal, and a clock phase detector for comparing logic level transitions of the input data stream with transitions of the extracted data clock signal and in response generating a delay adjust signal for defining the variable programmable amount of delay such that the transitions of the input data stream are substantially aligned with the transitions of the arbitrary clock signal.Type: GrantFiled: February 27, 2001Date of Patent: September 21, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Paul Alan Gresham
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Patent number: 6784706Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The method includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.Type: GrantFiled: December 20, 2002Date of Patent: August 31, 2004Assignee: Zarlink Semiconductor, Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius de Rijk
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Patent number: 6775685Abstract: An apparatus and method for generating the square of a non-linear encoded signal having a value and a segment number includes an offset generator, a multiplier and a shifter. The offset generator receives the value of the encoded signal and adds an offset value to it thereby to generate a multiplicand. The multiplicand is squared by the multiplier and the output of the multiplier is conveyed to the shifter. The shifter shifts the output of the multiplier in accordance with the segment number thereby to generate the square of the encoded signal. The offset, multiplying and shifting steps can be performed in a single clock cycle.Type: GrantFiled: September 29, 2000Date of Patent: August 10, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Robert G. Wood
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Publication number: 20040153894Abstract: A circuit for measuring the accuracy of a clock signal comprising has a first digital phase locked loop receiving an input signal and providing an output signal and a second digital phase locked loop receiving at its input the output signal from the first phase locked loop. One or more measurement terminals are internally connected to one of the phase locked loops to provide a measurement signal.Type: ApplicationFiled: January 21, 2003Publication date: August 5, 2004Applicant: Zarlink Semiconductor Inc.Inventor: Robertus Laurentius van der Valk
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Patent number: 6768723Abstract: A method of improving convergence of an echo canceller in a full duplex speakerphone, wherein the echo canceller includes LEC (Line Echo Canceller) and AEC (Acoustic Echo Canceller) portions, comprising the steps of capturing LEC coefficients during operation, storing the coefficients, and utilizing the stored coefficients as default values during start-up of a subsequent call. The method of the present invention reduces the overall convergence time of the echo canceller by alleviating the requirement to wait for a suitable reference signal in order to converge the LEC.Type: GrantFiled: December 2, 1999Date of Patent: July 27, 2004Assignee: Zarlink Semiconductor Inc.Inventors: Mirjana Popovic, Rob McLeod
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Patent number: 6757859Abstract: An encoder for turbo coded trellis code modulation comprises an encoder data block for storing incoming data, and at least two recursive systematic convolutional encoders, said convolutional encoders being connected to receive data in parallel from said encoder data block. The decoder also employs a parallel implementation.Type: GrantFiled: May 1, 2000Date of Patent: June 29, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Gary Q. Jin
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Publication number: 20040070005Abstract: A protection device provides to integrated circuits against high voltages. The diode includes a diode connected to provide a safe discharge path for the high voltage currents. The diode is configured so that in reverse bias breakdown occurs across an area portion of its active junction. The device can dissipate a large amount of ESD energy in a minimal area.Type: ApplicationFiled: April 30, 2003Publication date: April 15, 2004Applicant: Zarlink Semiconductor Inc.Inventor: Jonathan Harry Orchard-Webb
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Patent number: 6711537Abstract: A Comfort Noise Generation (CNG) system is provided for use in open systems where there is no predefined protocol for transmission of Silence Insertion Descriptor (SID) information from transmitter to receiver. The receiver enters an underrun condition in response to periods of silence, and in response generates comfort noise. According to the present invention, the computation of the level and spectral characteristics of the background of the speech signal is done within the receiver, thereby overcoming the lack of a protocol to transmit the SID information during silence periods. These characteristics are computed as a gain parameter and a set of Linear Prediction Coding (LPC) parameters which are applied to a filter which filters flat-spectrum noise in order to generate noise that sounds like the background noise of the speech signal.Type: GrantFiled: November 21, 2000Date of Patent: March 23, 2004Assignee: Zarlink Semiconductor Inc.Inventor: Franck Beaucoup
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Patent number: 6697423Abstract: A decision feedback equalizer is provided which is capable of canceling precursor Inter-Symbol Interference (ISI) even when knowledge of future data is unavailable. A novel DFE algorithm is utilized whereby the detection signal-to-noise ratio (SNR) is increased in two aspects: the precursor contribution is eliminated and the sampling location (relative to the channel response) is positioned at the maximum SNR location. As a result, the loop length for data transmission in a cable can be extended.Type: GrantFiled: October 10, 2000Date of Patent: February 24, 2004Assignee: Zarlink Semiconductor Inc.Inventors: Gary Q. Jin, Gordon J. Reesor
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Patent number: 6678275Abstract: A termination device for connection to a group of TDM (time division multiplexed) trunks is capable of sending cells over one or more links either individually or as part of an inverse multiplexed group. The device includes a Utopia interface for receiving an incoming cell stream, a buffer for storing incoming cells at specific memory locations identified by pointers obtained from a queue of available pointers, a round robin scheduler for sequentially assigning cells to links forming an IMA group or individually in the UNI mode, and a pointer queue for each channel address, the pointer queue indicating the location of the next cell to be transmitted for each virtual channel. An adaptive shaper determines when a stuff cell is inserted and a per link output circuit places cells on the links, which can operate in CTC or ITC mode. The device can operate in mixed mode where up to four IMA and/or up to eight UNI channels can be supported concurrently. The links assigned to the IMA or UNI channels is programmable.Type: GrantFiled: February 18, 2000Date of Patent: January 13, 2004Assignee: Zarlink Semiconductor Inc.Inventors: Marcel DeGrandpre, Alexandre Pires
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Patent number: 6674845Abstract: In an apparatus for supplying a tip and ring telephone line with voice band and broadband signals, a first pair of drivers supply at least DC signals to the respective tip and ring line components, and a second pair of drivers supply broadband signals to the tip and ring line components. Feed components combine the outputs of said respective drivers for the respective tip and ring components of the telephone line.Type: GrantFiled: June 21, 2001Date of Patent: January 6, 2004Assignee: Zarlink Semiconductor Inc.Inventors: Mark Ayoub, Rick Geiss, Chi-Keung Leung, Joe Lung
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Patent number: 6671327Abstract: In a method of transmitting data over a communications channel, at least some of the bits of an incoming bit stream are passed through a turbo encoder to generate turbo encoded output bits, and words corresponding to symbol points on a constellation in a trellis code modulation scheme are generated using at least the bits passed through the turbo encoder, possibly in conjunction with other bits that are not passed the through the turbo encoder. Typically, the turbo encoded bits are the least significant bits.Type: GrantFiled: May 1, 2000Date of Patent: December 30, 2003Assignee: Zarlink Semiconductor Inc.Inventor: Gary Q. Jin
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Patent number: 6661895Abstract: A zero-delay structure to be used in sub-band echo cancellation systems. In telecommunications, a delay is usually introduced in sub-band decomposition and/or sub-band reconstruction. This invention will help remove this. This structure not only removes the delay but does not sacrifice the performance of the echo canceller. It is to be used in combination with any sub-band-based echo canceller or wavelet echo canceller.Type: GrantFiled: October 7, 1999Date of Patent: December 9, 2003Assignee: Zarlink Semiconductor Inc.Inventors: Qu Jin, Kon Max Wong, Qiang Wu, Philippe Wu, Gordon J. Reesor
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Method to generate telephone comfort noise during silence in a packetized voice communication system
Patent number: 6643617Abstract: A method is provided for generating comfort noise in a packetized voice communication system having a transmitter and a receiver. The receiver is provided with a buffer for storing voice packets. The buffer is chosen to be of a predetermine size such that, upon halting the transmitter as a result of silence detection, the buffer is filled with actual silence samples from the transmitter. A comparator compares an output TDM sample pointer with a start of silence pointer of the buffer. In the event that the pointers are the same, silence is flagged and a random number generator loads numbers into the TDM sample pointer for outputting a random sequence of the silence packets to the telephone receiver.Type: GrantFiled: May 22, 2000Date of Patent: November 4, 2003Assignee: Zarlink Semiconductor Inc.Inventors: Robert Geoffrey Wood, Franck Beaucoup