Abstract: A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.

Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.

Abstract: A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error.

Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.

Abstract: A telephone subscriber line device for providing an interface between a legacy telephone circuit based on circuit-switched technology and a packet network has a legacy interface for connection to telephone circuit; a packet interface for connection to a packet network, processing circuitry for converting between legacy telephone signals and packet signals, and a cascadable expansion bus permitting multiple said devices to be connected to a common port on a packet network. Such a device is highly scalable.

Abstract: A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.

Abstract: A digital FM transmitter has a digital controlled oscillator for generating a modulated RF carrier. A digital signal processor receives digital input samples and generates a modulating signal for input to the digital controlled oscillator. A bandpass filter for filters frequency components of the modulated carrier outside a predetermined frequency band and supplies the filtered modulated RF carrier to an antenna.

Abstract: A time division multiplex switch supporting multi-rate input and output serial data streams has a double-buffered data memory with buffer extensions associated respectively with each portion of the memory. The extensions store residual data for a delay period after the main portion of the double-buffered data memory has switched.

Abstract: A device for forming an optical connection between an optoelectronic device and an optical fiber and for forming an electrical connection between the optoelectronic device and a substrate, a system including the device and materials, and methods of forming the device and system are disclosed. The device for forming an optical connection includes a—light transmission medium and electrical connectors, which are at least partially encapsulated. In addition, the device includes guide grooves configured to receive guide pins from a fiber ribbon connector, such that when the fiber ribbon connector is attached to the device, fibers of the ribbon align with the optoelectronic device via the light transmission medium.

Abstract: A method of detecting double talk condition in hands free communication devices is disclosed. In general, the method in accordance with the teachings of this invention detects double talk conditions based on inherent frequency response differences between the transducers used and acoustical effect on the spectrum of the returned echo signal. An input signal from a far-end talker and an input signal from the output from an echo canceler are received by the detector. K spectral subbands are created for each input signal. From this K subbands q subbands are selected based on inherent frequency differences between the far-end transducer and a near-end transducer. The spectral echo residual power is estimated at each subband. The estimated spectral echo power and the output signal from the echo canceler for a selected subband are compared to a predetermined threshold. Based on this comparison, it is determined whether double talk conditions exist based on the comparison.

Abstract: A FIR filter for use in an adaptive multi-channel filtering system, includes a first memory for storing data, and a second memory for storing filter coefficients. The second memory stores only non-zero valued coefficients or coefficients that are above a predetermined magnitude threshold such that the overall number of coefficients processed is significantly reduced.

Abstract: Disclosed is a non-linear echo canceller and method for cancelling echo during full duplex communication in a hands free communication system. An input signal from a far-end talker and an input signal from the output from an echo canceller are received. K spectral subbands are created for each input signal. The spectral echo residual power at each subband is estimated and compared to a clean signal power to calculate a signal to echo ratio. Gains are calculated based on each calculated ratio and non-linear echo is cancelled based on the calculated gains.

Abstract: A node in for connection to a synchronous packet network includes a packet switch and a physical interface for connection to the packet network. A phase locked loop arrangement for synchronization is integrated into the physical interface, the packet switch or both.

Abstract: A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.

Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.

Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.

Abstract: A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.

Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.

Abstract: The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL's loop filter is disabled. Reduce the PLL bandwidth and/or lower damping to let the PLL settle. Switch the PLL to final bandwidth and damping required by the application.

Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.