Abstract: A circuit and technique provided as part of an integrated circuit for assuring that the circuit's many bistable elements are properly initialized into their desired state when the power is turned on to the circuit. An initialization signal is developed for forcing the bistable element to their pre-determined states as the voltage of the power source is brought up from zero to its full value. This is accomplished by using another bistable element to monitor the rise in the supply voltage and turn off the initialization signal only after the supply voltage has risen well above the threshold voltage of the various bistable elements on the circuit. Hysteresis is provided in order to prevent the initialization signal from turning on if the supply voltage temporarily dips below that at which the monitor element turns off the initiation signal.

Abstract: Separate memory management units are described for use with a central processing unit to separately control expanding stack and data memory portions within a single logical memory segment. The stack and data portions are prevented from expanding into each other by a break register which contains an address between the two memory portions and is updated as the stack and data memory portions expand and contract. The stack memory management unit only is enabled when a portion of the memory is addressed on one side of the break value while the data memory management unit only is utilized when the address is on the other side of the break value.

Abstract: A thermally balanced leadless microelectronic circuit chip carrier in which the chip is mounted directly on a heat sinking member by means of a conductive stress relieving polyimide. The heat sinking member, which has a support surface for the chip and an extending threaded shaft, is held by a carrier member thermally compatible with the surface on which the package is to be used. The shaft passes through the carrier member and receiving surface to a heat sinking nut which holds the package to the receiving surface. Leads on the carrier member surface are used to connect the receiving surface to the wires bonded to the chip contacts.

Abstract: Microprocessor apparatus in which the CPU generates as an integral function memory refresh addresses for an external dynamic memory without degradation of CPU performance. The CPU architecture is optimized by dividing the CPU devices selectively into groups during different time periods by the use of switching devices in the internal bus structure.

Abstract: To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.