Abstract: A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.

Abstract: A learning TV is disclosed which enables the TV to learn and be remotely controlled by remote control signals generated from any remote control device produced by any manufacturer. The user is able to assign to each received remote control signal a particular function such as POWER ON/OFF, performed by the learning TV. To facilitate the user in programming the television during the learning mode, directions are provided to the user on the television screen instructing the user of the various steps required to properly program the television to learn the remote control codes and how to assign these codes to a particular executable routine of the learning TV.

Abstract: A mask value generator is used to produce a mask value for deencrypting encrypted instructions from a memory. This encryption mask generator can produce a encryption mask value from a seed value and a program counter value. The seed value can stored in a memory outside the core microprocessor. The encryption mask value can be used to deencrypt instructions in an "exclusive or" logic section.

Abstract: A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum number of clock cycles. Thus, for an n-bit counter which is partitionable into k subcounters, the counting functionality and operational speed of the counter may be tested in at most 2.sup.n/k +2 clock cycles, and the loading functionality of the counter may be tested in at most 2.sup.n/k +1 clock cycles.

Abstract: A method and apparatus for displaying a bar image in two colors on a screen of a cathode ray tube are disclosed. The device includes a first memory for storing the information to be displayed, including the first color, and a second memory for storing the screen addresses where the images are to be displayed in a second color. It also includes a microprocessor for selecting information from the first memory to be displayed at specific addresses on the screen. When the address for display is the same as one stored in the second memory, the microprocessor causes information to be displayed in the second color instead of the first color.

Abstract: A self-configurable clock circuit which automatically detects at power up whether an off-chip crystal oscillator is connected to an integrated circuit including the self-configurable clock circuit, and following such detection generates a system clock signal and a power on reset signal to be used by other circuitry included in the integrated circuit. If the off-chip crystal oscillator is connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a first signal generated from the off-chip crystal oscillator. On the other hand, if the off-chip crystal oscillator is not connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a second signal generated from an on-chip RC oscillator circuit.

Abstract: A mode control circuit is disclosed which generates a mode control signal in response to an illegal state detected as a combination of inputs and outputs. An illegal state is forced by the application of a fixed voltage to an output pin. The mode control signal is used to switch input-output signals of a megacell internal to an application specific integrated circuit to the output pins of the package so that testing of the megacell is facilitated.

Abstract: A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a computer system that employs a number of such peripheral circuits that are selectively rendered operable by the CPU, one at a time. The peripherals each include an interface that receives an initial data word from the CPU that identifies the peripheral circuit with which data is to be transferred by the CPU. Rather than all such peripherals in a computer system being powered-up in order to have their processors determine individually under software control whether they have been identified by the CPU, only a small hardwired interface circuit is so enabled. Once this interface circuit determines that the CPU desires to conduct data transfer with it, the main portion of the circuit, including its processor, is then powered-up.

Abstract: The present invention concerns a method of preventing the staining and voiding in an aluminum layer. This staining and voiding was found to be caused by cross-contamination of nitrogen from other processing steps in a multi-chambered wafer processing device. The present invention avoids the staining and voiding by introducing a pumping-out step of an aluminum layer sputtering chamber to remove some of the nitrogen from the aluminum layer deposition chamber before sputtering the aluminum layer onto the silicon wafer. Alternately, the temperature of the aluminum layer deposition step can be reduced to 310.degree. C. or less to prevent the staining or voiding.

Abstract: A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

Abstract: The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer.

Abstract: A method and apparatus for using multiple program counters to reduce the latency time of a computer in response to an interrupt or subroutine call using a memory with multiple memory locations for storing the multiple program counters and control means in order to choose which one of the memory locations is used as a current program counter. Additionally, the use of a memory location to store the starting address of the interrupt subroutine is also disclosed.

Abstract: A flag setting, reading and clearing circuit is described which includes self arbitrating logic to provide priority for the flag setting portion of the circuit over the flag clearing portion. The flag is set by a set flag signal generated by a portion of a computer system to which the flag setting, reading and clearing circuit is a part. The set flag signal sets the flag by latching the voltage level of a voltage supply to a node in the circuit. A read status signal then latches the voltage at the node to another location which other portions of the computer system can access. At the same time, the read status signal clears the voltage level at the node unless the self arbitrating logic prevents it from doing so. The self arbitrating logic prevents the clearing portion of the circuit from clearing the flag when the set flag signal and the read status signal are both activated or HIGH at the same time.

Abstract: An electronic circuit employed in a microprocessor system inserts a programmable number of wait states in a machine cycle of the microprocessor in response to a specific operational code of the microprocessor's instruction set being detected on a system data bus. A particular application of the wait state generation circuit is to provide enough time for a control signal to propagate along a plurality of daisy-chained peripherals before the microprocessor machine cycle ends. The wait state generation circuit may be provided as part of the microprocessor on a single integrated circuit chip.

Abstract: An electronic device receives data from an EEPROM by sending address information to it on one set of leads and receiving data back from it through a different set of multiplexed address/data leads. The electronic device also sends and receives data to and from a data path controller by sending address information and sending or receiving data information to or from it through the set of multiplexed address/data leads. Selection of which device, the EEPROM or the data path controller, to communicate with is made by the electronic device setting appropriate values for chip select and chip enable commands. Synchronization of the sending and receiving of the address and data information is accomplished by the use of address and data strobe signals generated by the electronic device and connected, as appropriate, with the EEPROM and data path controller.

Abstract: A semiconductor multi-device system incorporated on a single semiconductor chip is disclosed including a central processing unit, a bus, a plurality of peripherals, a plurality of on-chip data bus drivers connected to selected lines of the bus, and logic means for controlling the operation of the on-chip data bus drivers. The multi-device system of the invention is capable of interacting with off-chip components including an off-chip processing unit and off-chip peripherals. The off-chip components may also include a plurality of off-chip data bus drivers that drive data signals onto and off of an off-chip data bus. The on-chip and off-chip drivers must cooperate in order for data signals to transfer properly between the on-chip and off-chip components. The logic means of the invention is designed so as to minimize the logic necessary to cause the on-chip drivers and the off-chip drivers to cooperate properly.

Abstract: A circuit for transferring data from one bus system to another is disclosed. The circuit allows the write bus to perform write operations indiscriminately of any handshaking, wait states or other control signals which would otherwise reduce the bus efficiency of the system. Similarly, the read bus system has no handshaking or wait states but is provided with a data ready signal to indicate when valid data may be read. This circuit is used in applications where less than 100% data integrity is permissible.

Abstract: A filtering circuit and technique that is especially adapted to remedy the possibility of pulses from becoming corrupted when passing between a microcomputer unit and one or more peripheral devices, as they are communicated over an interconnecting cable, to the point of causing errors to occur in operation of the computer system. The specific circuit disclosed is especially adapted to operate with a small computer system interface ("SCSI") interconnecting bus standard. Adverse effects of false pulses created by voltage supply variations on the interconnecting cable and reflections of pulses along the cable due to impedance mismatches are remedied.

Abstract: A method and system for determining the bit patterns to be loaded into control registers of a specific electronic integrated circuit, including a computer software tool which accesses a table of register field bit pattern alternatives that can be loaded into the circuit in order to cause the it to operate in a selected manner. This table also contains English descriptors for each of the field choices so that the user may easily select the desired bit pattern for each field in order. Functional variables for a certain class of integrated circuits, such as those which operate as communications controllers, for example, are individually mapped into various control register fields in order that the computer system designer is led through the specific register choices which must be made so that one particular integrated circuit of this class will carry out the desired functions.

Abstract: An address detection circuit is described having a node A which is precharged to the voltage of a power supply and then discharged down to ground by a strobe signal if an address match occurs. An address match is detected when a nonconventional CMOS inverter which has its input connected to node A has its output go HIGH. The nonconventional CMOS inverter utilizes a device ratio between its P-mos transistor and its N-mos transistor of approximately 10 to 1 for a 1 micron CMOS process. Prior to the strobe signal discharging the node A to ground, the output of the nonconventional inverter is held to ground by a transistor which is switched OFF when the strobe signal discharging the node A to ground is initiated.