Abstract: In an environment where a contact of a mother board is connected to a logic HIGH level voltage through a strong pull-up resistor, and a corresponding contact of an add-in board is connected to an open-drain driver, such that a control line driven by the open-drain driver is provided through the two contacts in normal mode operation when the two contacts make electrical connection, a circuit to sense whether or not the contact of the add-in board is making electrical connection with the contact of the mother board includes a weak pull-down resistor connected at one end to a node connecting the output of the open-drain driver to the contact of the add-in board, and connected at the other end to a ground reference.
Abstract: A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region.
Abstract: A new technique for generating OSD characters is disclosed having a system architecture which utilizes a minimum of hardware and which is primarily implemented through software. The technique of the present invention incorporates the use of a microprocessor which is utilized to store and transfer video data to and from a plurality of logic circuits which make up the OSD system. One aspect of the present invention is directed to a clock switching device which drives both the CPU and other logic circuits of OSD system. The switching device is responsive to at least one control signal for providing an output clock signal which is switchable between two clock signals. Another aspect of the present invention is directed to a technique for altering the font size of the characters displayed on a kinescope. Specifically, the present invention is able to expand the width of the various characters displayed on the screen without altering the frequency of a DOT clock signal, as is done in conventional OSD systems.
Abstract: In a system for transmitting data employing a transmit FIFO and a transmitter, the quantity of data that has been written into the FIFO is monitored and a transmitter is caused to begin transmitting data from the memory when the quantity of data in the memory exceeds a predetermined level. An end of frame condition is detected and a transmitter is caused to begin transmitting data upon receipt of end of frame signal even though the quantity of data in the memory does not exceed the predetermined level.
Abstract: In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions concurrently while they are being fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.
Abstract: A single chip dual processor is implemented combining a microcontroller and digital signal processor. An unitary instruction set is utilized for programming both processors in one source program which is stored in a single external program memory. While compiling the source program, a compiler distinguishes which instructions are to be executed by which processor and designates each instruction to be stored in the appropriate memory space allocated to the processor which is to execute the instruction.
Abstract: Electrostatic discharge protection circuitry is used to protect a MOS feedback element placed between pins such as oscillator input and an oscillator output pins. The ESD protection circuitry may include a first metal-oxide-silicon field effect transistor whose source and gate are electrically connected to the oscillator input pin and whose drain is electrically connected to the oscillator output pin and a second metal-oxide-silicon field effect transistor whose source and gate are electrically connected to the oscillator output pin and whose drain is electrically connected to the oscillator input pin.
Abstract: A technique for accessing and refreshing memory locations within a plurality of electronic storage devices which need to be refreshed is disclosed. The technique allows for the accessing of memory locations within the plurality of devices row-by-row such that all memory locations having the same row address within each of the devices are accessed before a memory location with a higher row address is accessed. This accessing technique is implemented through the use of a newly designed address decoder architecture. Once data is stored within the memory locations in this manner, the refreshing technique refreshes only those rows within the plurality of devices which contain data.
Type:
Grant
Filed:
March 8, 1993
Date of Patent:
July 16, 1996
Assignee:
Zilog, Inc.
Inventors:
Asher Hazanchuk, Aleksander M. Movshovich
Abstract: A two-step flash ADC includes a MSB reference ladder having a first plurality resistors of resistance r and a second plurality of resistors of resistance R, serially connected together on an alternating basis starting and ending with one of the first plurality of resistors. A LSB reference ladder having a total resistance R.sub.L is initially connected across a predetermined (2r+R) leg of the MSB reference ladder. The resistances r, R, and R.sub.L are selected such that the effective resistance resulting from connecting the LSB reference ladder in parallel with a (2r+R) leg of the MSB reference ladder is equal to a (r+R) leg of the MSB reference ladder. In a first step of the two-step flash ADC, MSB reference voltages are picked-off the MSB reference ladder from actual or effective (r+R) legs of the MSB reference ladder, compared against an analog input voltage, and used to generate the most-significant-bits of a digital number corresponding to the analog input voltage.
Abstract: A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.
Type:
Grant
Filed:
October 7, 1994
Date of Patent:
March 12, 1996
Assignee:
Zilog, Inc.
Inventors:
Alex Gyure, John Berg, Damian Carver, Pete Manos
Abstract: An analog circuit implementing a continuous wavelet transform forms a multiplicity of analog wavelet outputs. These analog wavelet outputs can be used for data compression. This analog circuit is estimated to be about one-hundredth (1/100) the size and power of a digital wavelet transform circuit. Additionally, the analog wavelet outputs of the analog wavelet transform chip is directly determined without the loss of information due to the digital sampling.
Abstract: By monitoring various combinations of control signals generated by a microprocessor in a computer system in the first operational cycles after it is reset, a peripheral circuit sets itself to respond appropriately to control signals from the microprocessor according to any of several different protocols. For example, an instruction from the microprocessor to write to or read from the peripheral circuit is implemented over two control lines with one of several possible protocols. The circuit determines which protocol is being used each time the system is initialized and thereafter knows when a read or write operation is being performed. Another example is the different wait or acknowledge protocols that various microprocessors use.
Abstract: Data is stored in and read from a semiconductor memory system including multiple memory integrated circuits in data units commonly exchanged with a rotating memory device. One or more data units to be stored are clustered with a multiplicity of other data units stored in the semi conductor memory to form a cluster of data units. The cluster of data units is compressed, and the compressed cluster of data units is then error correction coded. The compressed cluster of data units is then stored in the semiconductor memory with a multiplicity of contiguous data bits being stored in a single memory integrated circuit. Data compression reduces the number of memory integrated circuits required, thereby reducing both cost and power consumption. Data is stored in and read out of the memory integrated circuits serially such that only a single memory integrated circuit is active at a time, further reducing power consumption.
Abstract: A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.
Abstract: A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.
Abstract: A computer process for developing a test program and data for use on automatic test equipment ("ATE") to test the logical function of actual integrated circuits. The separate trace files usually developed by the designer of a particular circuit in order to simulate the circuit's logical operation are utilized to produce the test program and data for controlling the ATE's testing of that circuit. The computer implemented process for doing so includes separate preliminary processing, related to the trace files but essentially unrelated to the particular ATE used, and post processing, for converting the intermediate results of the preliminary processing into a test program and data for driving a particular type of ATE. The process includes the use of common timing files for data from the plurality of trace files, and conversion of a binary integer representation of timing edges to ASCII characters with a significantly reduced number of bits.
Abstract: A central processing unit (CPU) and a dedicated pulse generating and demodulating logic circuit are used to both generate and demodulate a wide variety of pulse signals. Although the CPU exercises general supervision of the dedicated logic circuit, the circuit is arranged to perform most operations independently. Counters, registers and controlling logic generate a pulse stream. This same circuit, with the addition of edge detectors, demodulates (learns) the characteristics of an existing pulse signal in order to be able to generate a replica of that existing signal. An example application of the circuit is with television and other electronic equipment remote control units that include a learning capability.
Abstract: A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ("CPU") receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored.
Abstract: Pseudorandom values are produced using a memory and an arithmetic logic unit. The previous value is shifted four places to the left to form a shifted value. Next, the previous value is subtracted from this shifted value to form a subtracted value. The least significant bit of this subtracted value is complemented to form the new value.
Abstract: A microprocessor formed on a single integrated circuit chip has separate sets of terminals providing read and write control timing signals to external memory and input-output devices. The memory control timing signals are generated at a rate as high as the memory devices will allow. The input-output device timing signals are provided at a rate as high as the input-output devices will allow, usually significantly lower rate than that of the memory devices. This then allows the memory transactions to occur at a rate that does not need to be reduced because of slower input-output devices in the same system. The need for external logic is significantly reduced by providing the memory timing signals in a form that is actually input to the memory devices, and by including a capability of providing timing signals to a number of different types of input-output devices having different control signal timing protocol requirements. A computer system using such a microprocessor unit is also described.