Abstract: A digital electronic circuit for incrementing or decrementing a binary word one count at a time. Such a circuit has an application as an address counter wherein a block of addresses in memory are stepped through one at a time. Such an address counter is found, for example, in a direct memory access (DMA) computer system integrated circuit. The count is incremented or decremented by adding or subtracting, respectively, a one from the current binary count in order to obtain a new count. A carry chain used as part of such addition circuit is separated into at least two parts and a look-ahead chain is added to work in conjunction with the carry chain to anticipate certain changes without having to wait for the carry chain to be fully sequenced. This technique reduces the time necessary to calculate the carries in the addition or subtraction process and further allows some parallel operation of the two parts of the carry chain.

Abstract: A universal bus interface compatible with a number of different bus interface protocols is disclosed. In any given application, the control lines carrying signals by a processor are connected to the appropriate interface signal pins of the bus interface with all unused interface signal pins tied to their inactive level. The bus interface derives a strobe signal from the timing information carried by the control lines from the processor. The strobe signal derived by the interface controls data flow within a peripheral device or data flow between a peripheral device and a processor without the aid of any clock signals. A NAND-gate is used in the interface to derive the strobe signal from processor control signals. The NAND-gate comprises a number of inverters arranged in parallel each located close to an interface input pin to eliminate the need for any logic for driving the gate. The outputs of the inverters are connected to a common node to provide the strobe signal.

Abstract: The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

Abstract: A technique is disclosed for manufacturing an integrated circuit die which is capable of being packaged in any of two or more different package types having different arrangements of bonding posts. The circuit is laid out with redundant pads located at different places on the die so that one pad in each pair of redundant pads is accessible for bonding with posts in one package type, while the other pad in each pair of redundant pads is accessible for bonding with posts in another package type. Illustrative layouts are shown whereby various types of pads, e.g., power pads, signal input pads, signal output pads and bidirectional I/O pads, may be made redundant.

Abstract: The fill or empty level of a FIFO is detected and compared to a first request level for the direct memory access controller or the coprocessor. When the fill or empty level exceeds the first request level, notification to the DMA or the coprocessor is generated. The fill or empty level is also compared to a second request level and when such level exceeds second request level, notification to the CPU is generated. Thus, in most cases, the DMA or coprocessor is able to obtain control of the bus before the request level for CPU interrupt is reached, thereby preventing wasteful CPU intervention as well as FIFO overruns and underruns. In case the DMA or coprocessor is unable to obtain control of the bus before the request level for CPU interrupt is reached, CPU intervention is available as a last resort.

Abstract: In the serializer for converting parallel data into serial data, where the parallel data comprises normal characters all of the same length and a last character of a different length, the characters are each tagged by an extra bit as it enters a FIFO. This tag bit indicates the length of the character and is shifted along with the character as the character is shifted through the FIFO. The normal character length and the length of the last character are stored. As a character emerges from the FIFO, its tag bit identifies it as a normal character or as the last character. Such tag bit is used to select the correct character length in a counter. The character is loaded in a shifter which is controlled by the counter. Therefore, the shifter is controlled by the counter to shift the correct number of times in order to shift the character into a serial bit stream.

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents generated by electrostatic discharge through handling or otherwise, is provided by a circuit structure at each input pad of an integrated circuit chip. One such feature includes the use of a barrier layer of polysilicon material to make an electrical contact between source and drain diffusions of a protective transistor and their respective aluminum conductors, in order to increase the amount of current that can be handled at such contacts without the aluminum conductor fusing though a diffusion into the substrate. Another such feature is to provide an initial, and perhaps only, protective transistor that has a very narrow channel between source and drain diffusions to allow a reversible breakdown to reduce the voltage across it to within, or nearly within, the maximum voltage that the protected thin gate oxide transistor can handle without being damaged.

Abstract: A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.

Abstract: A system for detecting the presence of trailing zeros in a number. The number is divided into a plurality of consecutive groups, each group having an address. The system also determines the address location of the lowest order group which contains at least one non-zero bit and which precedes any trailing zeros of the number. Such group defines a target group. The system includes a first circuit for dividing the number into a plurality of consecutive words where each word contains more bits than any group. The first circuit also determines the lowest order word which contains one or more non-zero bits and which precedes any trailing zeros of the number. The system includes a second dividing circuit for dividing each word into a plurality of segments each having a number of bits equal to or greater than the number of bits in the target group.

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

Abstract: A technique for programming connections of conductors that is particularly adapted to be implemented as part of an integrated circuit so that a number of connections internal of the circuit can be made from outside the circuit in order to customize it after fabrication. A specific arrangement of five switching transistors is particularly advantageous for each cross-point of two conductors to be connected together in one of many possible ways. The desired switching arrangement at each cross-point may be programmed by use of the same conductors being interconnected to carry control signals from outside the circuit to a memory associated with each cross-point switching circuit. While these memories are being programmed, each cross-point is temporarily forced to a desired state for communicating the control signals from outside the circuit to the memories.

Abstract: A disk controller system utilizes a single state machine having random access memory which is loaded with program code to translate between computer data and signals obtained by reading from, or developed for writing onto, a magnetic disk in accordance with a selected data encoding technique. The encoding techniques that are discussed include FM, MFM, GCR and RLL. Different program code is loaded into the state machine's memory to make the controller operate with each of these techniques.

Abstract: A 32-bit central processing unit (CPU) having a six-stage pipeline architecture with an instruction and data cache memory and a memory management units, all provided on a single, integrated circuit (I.C.) chip. The CPU also contains means for controlling the operation of a separate I.C. chip co-processor that is dedicated to performing specific functions at a very high rate of speed, commonly called an extended processing unit (EPU). The EPU is provided with interface circuits that generate control signals and communicate them to the controlling CPU.

Abstract: The non-overlap clock circuit of this invention is responsive to a variable input signal for producing a first and second output signal that vary respectively with phases opposite to and the same as the input signal. The circuit comprises a NOR-gate with its first input connected to the variable signal input and its second input to the second signal output of the circuit. The output of the NOR-gate is the first signal output of the circuit. The circuit includes a first means such as an enhancement type FET having a gate and a main current path. The gate is supplied with a first output signal of the circuit and the main current path is connected between ground and the second signal output of the circuit. A second means such as a depletion type FET is also employed with its main current path connected between the variable signal input and the second signal output of the circuit. The second signal output of the circuit is thus driven by the variable input signal through the main current path of the second means.

Abstract: From an input signal, a buffer circuit derives an output signal which changes in logic state in synchronism with the rising edges of a first clock and whose value follows the input signal but in opposite logic state. The first clock directly drives the buffer output through a first transistor whose gate is controlled by the output of a NOR-gate. The buffer output is connected to ground through two FET's whose gates are controlled respectively by the first clock and the input signal as sampled by a second clock. The buffer output after being delayed and the input signal as sampled by the second clock are applied to the inputs of the NOR-gate. By adding an FET between the gate of the first transistor and the output of the NOR-gate the bootstrap action caused by the gate-drain parasitic capacitance of the first transistor reduces the delay between the rise of the buffer output and the rising edge of the first clock.

Abstract: A method of thermally oxidizing polycide substrates in a dry oxygen environment as well as a MOSFET structure provided by the method are disclosed. The method includes heating a plurality of polycide substrates to temperatures greater than about 800 degrees Centigrade in a dry oxygen environment, and introducing into the environment an amount of a halogenated alkane gas sufficient to induce oxidation.

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

Abstract: A method of improving film adhesion during the fabrication of thin film integrated circuits is disclosed. The method includes the steps of depositing a metallic silicide on a substrate and then implanting selected ions at predetermined doses and energies into the silicide layer, whereby tensile stress generated during fabrication processes is reduced. In one embodiment of the invention, the substrate is provided with a polycrystalline silicon layer and the silicide is of the structure MSi.sub.x, where M is a refractory metal and x is greater than 2. Preferred doses range from 10.sup.15 to 10.sup.17 cm.sup.-2, while preferred energies range from 40 to 150 keV.

Abstract: A special reset function is provided in the CPU, using the same control input to the CPU as the normal reset, to reset only the program counter to facilitate the use of a single CPU in a microprocessor development system.

Abstract: To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.