Abstract: An electronic device receives data from an EEPROM by sending address information to it on one set of leads and receiving data back from it through a different set of multiplexed address/data leads. The electronic device also sends and receives data to and from a data path controller by sending address information and sending or receiving data information to or from it through the set of multiplexed address/data leads. Selection of which device, the EEPROM or the data path controller, to communicate with is made by the electronic device setting appropriate values for chip select and chip enable commands. Synchronization of the sending and receiving of the address and data information is accomplished by the use of address and data strobe signals generated by the electronic device and connected, as appropriate, with the EEPROM and data path controller.

Abstract: The present invention concerns a method for doping a polysilicon layer with phosphorous in which phosphorous oxychloride is supplied to the silicon wafer near the beginning of the oven temperature ramping of the silicon wafer. By introducing the phosphorous oxychloride earlier than in prior art methods, the present invention can reduce the poly rho and poly rho sigma of the doped polysilicon layer. Alternatively, the root DT of the diffusion of the doped material in the doped silicon region on the silicon wafer can be reduced, which helps to maintain the junction depth of the doped silicon region.

Abstract: The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer.

Abstract: A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM.

Abstract: An existing integrated circuit layout is modified or revised in order to shrink it, update it, modify it for merger with another circuit on a single chip, or the like, in a manner which assures, prior to implementing the modified layout in an integrated circuit chip, that the electronic circuit implemented by it has not inadvertently been modified in the process. Data of the existing layout is first run on a net list extractor computer software program in order to determine its net list. After the layout is modified by usual computer techniques, the modified layout data is run on the extractor program to obtain another net list, and the net lists are then compared for any undesired differences. Once the modified layout has been determined to be free of any such differences, a set of masks are made from the modified database. The masks are used then used to manufacture the integrated circuit.

Abstract: Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

Abstract: A number of stand-alone devices are connected in a sequence in a predetermined order for reading information from a bus. The devices read information from the bus one at a time and in the predetermined order in response to a signal.

Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes.

Abstract: An unsigned integer multiply/divide circuit is implemented with an unconventional non-restoring division algorithm which always subtracts the divisor from the partial dividend regardless of whether the divisor is greater than the partial dividend or not, a hybrid carry lookahead and carry select adder construction where both portions run in parallel, and control lookahead features which avoid interim calculation wait delays. The division algorithm is further modified in order that the same hardware configuration primarily consisting of storage registers, an adder, a multiplexer, and a shifter can be used for both multiplication and division operations.

Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes.

Abstract: A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM.

Abstract: Initial data and/or control bits of registers within a digital integrated circuit are loaded from a non-volatile and/or read-only memory provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

Abstract: A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.

Abstract: The device of this invention controls a cathode ray tube (CRT) in order to display desired images on a selected region of the screen. Locations on the screen are identified by horizontal and vertical addresses. The device comprises means for storing information to be displayed on the screen of the cathode ray tube and a control means. The control means selects information for display and generates a display control signal for controlling the cathode ray tube. The display control signal causes the cathode ray tube to display the selected information and also indicates a predetermined vertical or horizontal address. When the display control signal indicates a horizontal address, the control means displays selected information only in the region of the screen above or below the horizontal address and not in the remainder of the screen.

Abstract: A domino-logic decoder which decodes an input in an amount of time substantially independent on the bit size of the input. An address is input to a stack of at least two individually gated transistors in the decoder. A first node at one end of the stack is connected to a charge restoring transistor and a strobing transistor, both coupled to a strobe signal. A second node coupled to the strobing transistor provides the decoder output and operably indicates that a particular portion of the decoder has been selected. During operation, the first node is charged and the second node is isolated from the first node by the strobing transistor. After the inputs have fully charged the input transistors and a path to ground is formed, the first node will be discharged. The second node is discharged across the strobing transistor during the strobe phase, indicating that a particular decoder portion has been chosen. Body effect is also eliminated.

Abstract: A circuit, which may be included as part of an integrated circuit chip including a microprocessor or other device needing initialization when being powered up, generates a reset signal at a time determined by the voltage rise characteristics of the power supply to the device when either initially turned on to the device or recovering from a voltage dip. A power supply sensing node of the circuit is initially discharged to ground potential in order to eliminate any effect of a charge on the node on the timing of the reset signal, such as might be generated by an ambient electromagnetic field.

Abstract: A circuit has a mask option for choosing between a crystal or an RC oscillator. The RC oscillator is completely fabricated on an integrated-circuit chip and includes a charging path, a discharging path, and a capacitor coupled at a node. The alternating charging and discharging of the node produces the oscillating output voltage signal at certain frequency. The oscillation frequency may be trimmed by coupling a single optional external resistor to either the charging or discharging paths, thereby reducing the output oscillation frequency.

Abstract: In an oscillator circuit, a high gain, high power driver is placed in parallel with a standard low gain, low power driver for driving the oscillator output. A control signal is derived from the output of the oscillator circuit and fed back to control the high gain driver. After the circuit output has achieved stable oscillations for a predetermined time period, the high gain driver is turned off. Employment of the high gain driver ensures high start-up ability. The overall power consumption remains low since the high gain driver is turned off after stable oscillations have been achieved.

Abstract: A peripheral device containing a control circuit with internal timing which enables it to independently adjust the timing of an interrupt acknowledge cycle. The circuit senses a timing signal from the CPU and asserts a control signal to suspend the operation of the CPU for a predetermined period of time. The predetermined period of time is customized to the peripheral so that when the CPU is re-activated and reads from the bus, a valid interrupt vector will have been put out by the peripheral.

Abstract: A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1.5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.