Abstract: An extraction system detects a voltage stored in a capacitor and then extracts energy from the capacitor when the voltage falls below a predetermined value. The capacitor may be an ultracapacitor formed in silicon or another semiconductor material, and the predetermined value may equal or be based on a minimum operating voltage of a load driven by the ultracapacitor. Once the energy is extracted, the system converts the energy into a voltage sufficient to continue driving the load. Energy extraction may be performed by a variety of circuits including a linear regulator, a switched capacitor voltage converter, an adiabatic amplifier, and a DC-to-DC boost converter. The system may further include a monitoring circuit which detects dynamic changes in the converted ultracapacitor voltage over to maintain the operating voltage of the load.

Abstract: An apparatus and method for soft shadow calculations, the method including dividing an area light source into a patch of points, obtaining a packet of points on a surface that is subject to illumination by the patch of points, determining a form-factor value for each of the points in the packet of points; and simultaneously performing adaptive soft shadow calculations for each of the points in the packet based on the point in the packet having the greatest form-factor.

Abstract: A packet is received from a network at an out-of-band (OOB) network interface of an OOB platform switch of a computer system. A destination of the packet is identified. A next hop is determined along a path the packet may be routed to reach the destination. The packet is forwarded to the next hop via the OOB network interface by the OOB platform switch.

Abstract: A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on a probe channel and a request message on a second channel from one of the plurality of caching agents, and maintaining an open status for the miss request until the requesting cache agent receives the data or an ownership indicator.

Abstract: A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

Abstract: An online shopping basket is acquired by a buyer from an online store and is customized according to rules specified by the buyer. The buyer places zero or more items in the online shopping basket(s) before they are given to at least one shopper by the online store. The shopper(s) may further customize the online shopping basket(s) with rules that do not conflict with those specified by the buyer. The shopper(s) then place zero or more items in the online shopping basket(s) and return the basket(s) to the online store. Multiple online shopping baskets are merged into a single basket, and the buyer reviews the items in the merged online shopping basket and adds or removes items as necessary. The buyer then purchases the remaining items from the online store.

Abstract: Methods and apparatus for remotely managing a computer are disclosed. For example, a remote management agent is provided for use in a computer having a processor. The example remote management agent includes a communication agent in communication with the controller to contact a server before an operating system is loaded on the computer to obtain an initialization packet from a server and an initialization packet loader in communication with the controller to load the initialization packet in a protected memory area of the computer, before the operating system is loaded. The remote management agent also includes a monitoring agent, not associated with the operating system, in communication with the controller to monitor the computer for a communication from the server and a command line interface agent, also not associated with the operating system and in communication with the controller to interpret and respond to the communication from the server.

Abstract: Briefly, in accordance with one embodiment of the invention, an ad-hoc network comprises nodes. A sub-set of the nodes provides a backbone for communication between nodes in the ad-hoc network. At least some of the nodes in the backbone are selected to be a router based at least in part on a metric of the node.

Abstract: A mobile medication device including a timekeeping unit, which may be a wrist watch and may include a microprocessor, to track a plurality of time events associated with a plurality of medications to given to a user, wherein the time events may be specific times at which a particular medication is to be taken by the user, and may also include additional events such as a predetermined time prior to when the user is supposed to take a medication.

Abstract: A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free running clock that may be passed serially through a subset of memory units in the architecture. Sending of data is delayed over the point to point links based on proximity of the memory units to the buffer chip to accommodate delay in the multidrop clock signal.

Abstract: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: An amplifier circuit receives a phase modulated signal at an input node. The power supply terminal of the amplifier circuit is modulated in accordance with an amplitude envelope signal. The voltage on the power supply terminal is modulated using one or more linear regulators depending on the magnitude of the envelope signal.

Abstract: A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.

Abstract: Handshaking protocols, techniques, and structures are presented for use in implementing closed loop MIMO using explicit feedback in a wireless network.

Abstract: A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include processor circuitry and interface circuitry. The processor circuitry may include a plurality of processor cores. The interface circuitry may be capable of communicating in accordance a plurality of different protocols. At least one of the processor cores may be capable of issuing a command to the interface circuitry to communicate in accordance with at least one of the plurality of different protocols that corresponds to the selected mode of operation of the integrated circuit.

Abstract: Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of interfacing with the associated device. The device driver periodically monitors usage of the processors in the system and pins a processor to execute the interrupt handler of the device driver based upon the monitored usage. If the usage of the pinned processor exceeds that of one or more of the other processors, the device driver may pin the interrupt handlers to a different, lower utilized processor.

Abstract: A method and an apparatus to reduce electromagnetic interference (EMI) have been presented. In one embodiment, the method includes using a first clock signal to create a second clock signal having a fundamental frequency lower than a frequency of the first clock signal, wherein the first clock signal is used to transmit data from a chip within a chip set to an interconnect. The method may further include outputting the second clock signal to the interconnect via a data channel of the chip as a forwarded clock signal. The signal power may be redistributed to lower fundamental frequency to reduce EMI emission from the system. Other embodiments have been claimed and described.

Abstract: An apparatus, comprising: a first oscillator made from piezoelectric material to oscillate at a first frequency; a second oscillator to oscillate at a second frequency; a comparator to compare the first frequency to the second frequency; and a controller to change the first frequency in response to the comparing of the first frequency to the second frequency.

Abstract: A wireless station utilizes available metrics to determine whether to request a direct link with another wireless station.

Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: A method may include partitioning a plurality of processor cores into a main partition comprising at least one processor core capable of executing an operating system and an embedded partition comprising at least one different processor core. The embedded partition may be capable of: receiving a write request to write data on a target storage device; communicating with a remote system coupled to the embedded partition and remapping data corresponding to said write request to the remote system; detecting an error when attempting to write data to the storage device, leaving uncommitted data directed to the target storage device; and communicating with said remote system to retrieve the uncommitted data and writing the uncommitted data to the target storage device. The embedded partition of this embodiment may also be capable of performing these operations, at least in part, independently of said operating system being executed on said main partition.

Abstract: A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.

Abstract: A user interface enables the display of browser information in a space conserving fashion. A plurality of icons may be displayed along a bar adjacent a browser display window. When an icon is selected, an appropriate panel may be displayed. A uniform resource locator text entry block may only be displayed when an appropriate icon is selected. Thus the extra space that is lost through the display of the text entry block is only encountered when the user actually needs to make a uniform resource locator text entry.

Abstract: Embodiments of methods and apparatus for providing a cooperative relay system associated with a broadband wireless access network are generally described herein. Other embodiments may be described and claimed.

Abstract: In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device controller. The standard block device command is to invoke functionality from the device controller unrelated to the standard block device command. The functionality invoked by the standard block device command is performed by the device controller.

Abstract: Training symbol formats are provided for use in a MIMO based wireless communication system that uses adaptive power loading. In at least one embodiment, a training symbol format is used that is capable of enhancing training symbol signal to noise ratio (SNR).

Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.

Abstract: Some aspects provide determination of a debug event, selection of a controller context based on the determined debug event, and execution of the selected controller context. The debug event may be associated with a microprocessor, and the controller context may be selected based on predetermined associations between a plurality of debug events and a plurality of controller contexts.

Abstract: Power is applied to a voltage supply. A signal that indicates reduced work capability in an integrated circuit (IC) that is being powered by the voltage supply is generated based on workload demand or conscious power and performance tradeoffs. This signal is applied to increase the power efficiency of the voltage supply, while the supply is powering the IC in its reduced work capability state.

Abstract: Embodiments of a high-linearity low-noise amplifier (LNA) and method are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier and a common-gate stage. The common-gate stage is dynamically biased based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage.

Abstract: A method includes receiving a sequence of samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes selecting a filter from a bank of low pass filters based on the selected re-scaling factor, and low-pass filtering the sequence of samples with the selected filter. The method further includes up-sampling the low-pass-filtered sequence of samples by a factor M with a polyphase filter bank having a windowed sinc(t) characteristic to the up-sampled sequence of samples, and down-sampling the polyphase-filtered sequence of samples.

Abstract: An apparatus includes a plurality of output filters. Each output filter is to provide a respective output power signal at a respective voltage level. The apparatus also includes a plurality of power multiplexers. Each power multiplexer corresponds to a respective one of the output filters and each has a respective output coupled to an input of the respective one of the output filters. Each of the power multiplexers has a plurality of inputs. The apparatus further includes a plurality of power cells. Each power cell is coupled to a respective input of at least some of the power multiplexers. In addition, the apparatus includes a control unit to control the power multiplexers to selectively establish a connection between the output of each power multiplexer and at least one of the inputs of the power multiplexer.

Abstract: A power amplification system includes functionality for measuring and compensating for distortion and non-linearity in a power amplifier (PA). The compensation process may be performed repeatedly (or continuously) during the operational life of the PA to adapt to changing gain characteristics of the PA.

Abstract: Apparatus and systems, as well as methods for using them, may include launching a pulse into an input port of a quarter-wave directional coupler having an thru port and an isolated port, and receiving a leading edge of the pulse as a voltage spike at an output port of the coupler. A switch may be activated to couple a pulse source to the input port. The impedance of the coupler may be selected to match the resistance of the switch added to the impedance of a charge line included in the pulse source.

Abstract: Power management commands from virtual machines (VMs) in a VM environment may be trapped by a VM monitor. Depending on the current power states of the other VMs in the VM environment, the VMM may emulate increase or decrease in available resources as applied to the VM issuing the power management commands. The VMM may modify the actual hardware resources available in a platform when such modification may not affect the current power states of the VMs in the VM environment.

Abstract: A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions.

Abstract: A device and system are disclosed. In one embodiment the device comprises a primary display unit, a base unit coupled to the primary display unit, and a touch-sensitive secondary display unit, coupled to the base unit, operable to receive input from a user and display information for the user.

Abstract: A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one embodiment of the invention, an access point may preemptively broadcast an alternate channel to switch to, along with an indication of the beacon timing for the alternate channel, prior to any catastrophic interference. The access point may switch to the alternate channel in the event of interference on the original channel without attempting to broadcast the alternate channel during the interference event. A mobile user may then know in advance of the interference event which alternate channel the access point switched to and may switch to the alternate channel.

Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.

Abstract: A method, apparatus, and signal-bearing medium for allowing participants to exchange information regarding a program. The program may be a joint-development program in which the participants are participating, and the information may be confidential information regarding the program that belongs to the respective participants.

Abstract: Embodiments of the invention relate to integrated chemiluminescence devices and methods for monitoring molecular binding utilizing these devices and methods. These devices and methods can be used, for example, to identify antigen binding to antibodies. The devices include both a chemiluminescence material and a detector integrated together.

Abstract: Systems and methods provide automatic switching of display update properties such as screen resolution, pixel depth, and refresh rate in response to a power management event. The display update property may be decreased when power is switched from AC power to DC power, for example, when the system is unplugged from a wall outlet and is running on battery power.

Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract: A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first process. The file system integrity validation occurs independently of booting the host machine.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.

Abstract: A circuit and method provides subcarrier puncturing by placing no information in subcarriers that suffer from channel impairments where they cannot deliver information. If no energy is placed in these subcarriers, then the transmitted power may be re-allocated to the information carrying subcarriers to increase the Signal-to-Noise Ratio (SNR) at the target node. Or, energy may be place in subcarriers that suffer from channel impairments, but the PAPR of the OFDM symbol may be reduced.

Abstract: An encoded input bit stream is interleaved across a number of symbols having different bit sizes in a manner that ensures that the bits assigned to each symbol from the bit stream are separated by a minimum separation. In this manner, bits that are adjacent within the bit stream do not get assigned to the same symbol.