Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract: Method and apparatus to manage power for a communication device having multiple radios are described.

Abstract: An interactive video system is disclosed that processes a video data stream and an associated data stream corresponding to the video data stream. The interactive video system displays a video image defined by the video data stream on a display device and performs interactive command functions specified by the associated data stream. The interactive command functions include commands that specify placement of a video display window, commands that specify parameters of graphical objects that are associated with the video image and commands that specify pixel data or graphics description for the graphical object and commands for placement of selection windows and that specify interactive functions for the selection windows.

Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.

Abstract: According to an embodiment of the invention, a method and apparatus for session key exchange are described. An embodiment of a method comprises requesting a service for a platform; certifying the use of the service for one or more acceptable configurations of the platform; and receiving a session key for a session of the service, the service being limited to the one or more acceptable configurations of the platform.

Abstract: Reducing memory access bandwidth consumption in a hierarchical packet scheduler. A hierarchical packet scheduler is maintained, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers, wherein one or more threads serve each level. Scheduling operations are performed at each scheduler of the hierarchical packet scheduler by reading a portion of scheduler state from external memory.

Abstract: A method comprising introducing an organometallic precursor according to a first set of conditions in the presence of a substrate; introducing the organometallic precursor according to a different second set of conditions in the presence of the substrate; and forming a layer comprising a moiety of the organometallic precursor on the substrate according to an atomic layer deposition process. A system comprising a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor comprising a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures formed in a plurality of dielectric layers formed on the substrate and each of the plurality of interconnect structures separated from the plurality of dielectric layers by a barrier layer formed according to an atomic layer deposition process.

Abstract: A device for mapping and demapping cells in an orderly manner is provided. The device employs a channel identifier and in certain configurations a buffer and series of stages to provide for relatively ordered, predictable mapping and demapping of data, such as virtual concatenation data.

Abstract: Methods and apparatuses for integration of authentication and policy compliance enforcement. An enforcement agent may reside on a device. If an access assignment is provided to the device in conjunction with authentication, authorization to use the access granted may be restricted by the enforcement agent. In one embodiment a reduced-access assignment is made by an authenticator.

Abstract: Apparatuses and methods for determining and applying receiving sensitivity threshold and/or energy detection threshold values for one or more nodes of a wireless network cell are described herein.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.

Abstract: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

Abstract: A method for forming electronic inductors. A model of the desired shape of the inductor is first formed in wax or other soft material. It is compressed in a block of magnetically permeable material and then heated to remove the wax shape. The resultant cavity in the shape of the inductor is filled with conductive material to form an inductor within the magnetically permeable material block.

Abstract: An optical network, which includes edge and switching nodes, optically communicate information formatted into bursts that are included in one or more optical channel transport unit (OTU) frames that are based on ITU-T recommendation G.709. The overhead portion of the OTU frame can include all of the fields defined in the G.709 standard, except that the two reserved bits are used to define an OTU frame type. When the FEC function is not used, the OTU frame can be arbitrarily partitioned to carry optical burst information. The information can be either control and/or data bursts or metadata related to the optical network and/or optical burst flow. When the FEC function is used, the OTU frame is used to include optical control or data bursts or optical metadata in the payload portion of the G.709 OTU frame.

Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.

Abstract: A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.

Abstract: An electrical connector to be electrically disposed between a first circuit board and a second circuit board to electrically couple the first circuit board with the second circuit board is disclosed. The electrical connector may have an electro-optic modulator to modulate optical signals based on electrical signals exchanged between the first and second circuit boards through the electrical connector. Systems incorporating such electrical connectors, and methods of using the electrical connectors and systems, such as for debug, are also disclosed.

Abstract: An embodiment of the present invention may comprise a method to calculate current bandwidth usage by existing connections in a switching fabric between endpoints in a device, calculate available bandwidth for a new connection, and select a path from the multiple paths based on the bandwidth calculations. Some embodiments may be a device, comprising a port to connect the device to paths in an advanced switching fabric, a module to determine current bandwidth usage on the paths, calculate a cumulative bandwidth usage on the paths, calculate available bandwidth for a new connection, and select one of multiple paths available for the new connection.

Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.

Abstract: Systems and methods of managing threads provide for selecting a thread for execution and identifying a target performance state of a processor core based on the thread. Identifying the target performance state may include applying a priority of the thread to a mapping policy to obtain the target performance state. In one embodiment, a transition of the selected core to the target performance state can be initiated and the thread can be scheduled for execution by the processor core.

Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.

Abstract: A voltage regulator provides an operation voltage to a memory system and a transient voltage supply adjusts the operation voltage provided by the voltage regulator during transient events of the memory system.

Abstract: A nano-sized metal particle composition includes a first metal that has a particle size of about 20 nanometer or smaller. The nano-sized metal particle can include a second metal that forms a shell about the first metal. A microelectronic package is also disclosed that uses the nano-sized metal particle composition. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes the nano-sized metal particle composition.

Abstract: Techniques are described herein that can be used to control which packets or other data are able to be processed or otherwise utilize logic of a computing device. For example, a signature may be associated with a packet or other data received from a network. The signature and the packet or other data may be transferred to the computing device. Prior to the computing device deciding whether to allow logic such as hardware or software to use, process, or act using the packet or other data, the computing device may inspect the signature to determine if such signature permits such packet or other data to be used, processed, or acted upon.

Abstract: Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output electrical signal by the comparator upon comparing the voltages, latching the output electrical signal by a flip flop, generating an electrical refresh pulse by a refresh pulse generator upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes in the non volatile memory and generating an electrical sample pulse by a sample pulse generator, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal.

Abstract: Embodiments include systems and methods for management of RPIPES in a Wireless Universal Serial Bus (WUSB) environment comprising at least one WUSB device. RPIPE management computer code is executed to perform RPIPE management functions including monitoring RPIPE memory usage, and storing transfer requests in a queue in memory of the host machine while awaiting availability of Host Wire Adapter (HWA) memory.

Abstract: A method to couple a module to a board including power circuitry. The method includes detecting a module's power requirements before providing payload power to the module and routing a regulated power level to the module via at least one power feed based on the detected power requirements. The regulated power is provided by the board's power circuitry.

Abstract: Methods and apparatuses for error diffusion for display frame buffer power saving are described herein. According to one embodiment, pixels of a color plane of image data are stored in a first segment and a second segment of a frame buffer during a normal power state. During a low power state, an error diffusion operation is performed on the pixels to reduce a color depth of the pixels. Thereafter, at least a portion of the pixels with reduced color depth is stored in the first segment of the frame buffer during the low power state without accessing the second segment of the frame buffer. Other methods and apparatuses are also described.

Abstract: The present invention relates generally to automatic control of software application programs and image analysis and, more specifically, to analyzing graphical component, an execution scenario script, and a playback component. The recording component is adapted to capture user input data and images displayed by the graphical user interface during a recording phase of execution of the application program, and to analyze the captured user input data and displayed images to generate an execution scenario (script) during the recording phase. The execution scenario may be written in a selected high level language (e.g., XML).

Abstract: In one embodiment, a method is provided. The method may include determining if electromagnetic interference (EMI) is emitted by a device in one or more regions of an electromagnetic spectrum occupied by other users, and if it is determined that EMI is emitted by the device in one or more regions of the electromagnetic spectrum occupied by other users, reducing the EMI in the one or more regions, and increasing the EMI in one or more other regions unoccupied by the other users.

Abstract: In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

Abstract: A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user selected time window. A corresponding position in a register is updated to reflect the value of the transaction identifier. Subsequently, after the expiration of a counter, the corresponding position in the registers is compared to other predetermined positions in other registers to determine if the transaction identifier has been used (reissued). Otherwise, a possible hang condition might have occurred.

Abstract: An embodiment of the present invention provides an apparatus, comprising a wireless station operable in a wireless local area network, the wireless station capable of automatic discovery of other stations in a basic service set (BSS) which are capable of supporting direct link setup (DLS).

Abstract: A method for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The method is implemented via an apparatus that enables connectors to be automatically inserted into mating connectors on a circuit board device under test (DUT). Connectors may be automatically inserted along 1-4 axes. The apparatus includes replaceable probe/connector plates that are DUT-type specific, as well as DUT-type specific side access units. The apparatus may also be used for inserting memory devices and microprocessors, and further enables peripheral devices to be operatively coupled to expansion bus connectors on the DUT. In one embodiment, a single actuator is employed to actuate up to four insertion axes simultaneously.

Abstract: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

Abstract: Methods and an apparatus for generating a speculative helper thread for cache prefetch are disclosed. The disclosed techniques select spawn-target pairs based on profile data and a series of calculations. Helper threads are then generated to launch at the selected spawn points in order to prefetch software instructions (or data) for a single-threaded software application. The generated helper threads are then attached to the single-threaded software application to create a multi-threaded software application.

Abstract: Secure communication from one encryption domain to another using a trusted module. In one embodiment, the invention includes receiving encrypted streamed content encrypted with a first key, generating a substitution key stream based on the first key and a second key, generating a transposition key stream based on the first and second keys, and simultaneously decrypting and re-encrypting the encrypted streamed content using a combination of the substitution and transposition streams to produce re-encrypted streamed content encrypted with the second key.

Abstract: Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

Abstract: When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

Abstract: The present disclosure relates to resource management of memory using information regarding the physical state of the memory device(s), and, more specifically, to attempting to reduce the heat dissipation of a memory device by managing the contents of the memory device.

Abstract: Devices in an Advanced Switching (AS) fabric may include state machines for controlling the generation and transmission of flow control (FC) update data link layer packets (DLLPs) between link partners. A link partner may use the state machine to generate flow control update DLLPs for all available virtual channels (VCs) and transmit the FC update DLLPs contiguously to prevent any given VC from failing to perform an FC update refresh within an FC update timeout period due to injection of large packets (e.g., AS transaction layer packets (TLPs)) between the FC Update DLLPs.

Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

Abstract: A method for an extended precision integer divide algorithm includes separating an L-bit integer dividend into two equal width integer format portions, a first portion including lower M bits of the integer dividend and a second portion including upper M bits of the integer dividend, where M is equal to ½ L. An N-bit wide integer divisor is converted from an integer format into a floating point format divisor. The first integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a first floating point quotient, which is converted into a first integer format quotient. The second integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a second floating point quotient which is also converted to a second integer format quotient. Then first and second integer format quotients are summed together to generate a third integer format quotient.

Abstract: According to one embodiment a broad-angle multilayer (ML) mirror system is disclosed. The ML mirror includes a multiple layer structure configured to provide uniform reflectivity over a wide range of angles with small phase shifts.

Abstract: A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.

Abstract: A method and architecture for enabling interaction between a remote device and a host computer. A service provided by the remote device is discovered, and a description pertaining to the service is retrieved by the host computer. A network communication link is the established between the remote device and the host computer based on connection information provided by the description. Host-side and client-side software service modules are run on the host and remote devices to enable interaction between the devices using a service protocol that is specific to the service. Various service protocols are provided, including a display service protocol and an input service protocol. Using commands provided by each protocol, the host computer is enabled to control the service remotely by pushing data and appropriate commands to the remote device, whereupon these commands are processed by the client-side service module to perform service operations that employ the sent data.

Abstract: A test pin includes a compression element (110), a first tip (120) physically coupled to a first end (111) of the compression element, a second tip (130) physically coupled to a second end (112) of the compression element, a first arm (140) physically coupled to a first side (121) of the first tip, and a second arm (150) physically coupled to a second side (122) of the first tip.

Abstract: An apparatus, system, and method is provided including a plurality of test pins, a static dissipative layer having a plurality of openings, and a plurality of support features coupled to the static dissipative layer to movably support the static dissipative layer at a first and a second relative position. The support features enable the static dissipative layer to make initial contact with terminals of a component to be tested to discharge static, if any, built up at the terminals of the component while the static dissipative layer is supported at the first relative position. The support features also enable the static dissipative layer to expose the test pins through the openings to make contact with the terminals of the component after the static dissipative layer had made initial contact with the terminals of the component at the first relative position.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to pixelated masks for high resolution photolithography.