Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Method of enabling solder deposition on a substrate and electronic package formed thereby
    Patent number: 7538429
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Charavana Gurumurthy
  • Method and apparatus to provide variable gain in a radio receiver front end
    Patent number: 7539471
    Abstract: An RF receiver front end includes a variable gain low noise amplifier and/or a variable gain mixer to provide gain variability in the receiver. This gain variability may be used during, for example, automatic gain control operations. In at least one embodiment, the variable gain LNA is a broadband device that is capable of supporting multiple wireless standards.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Jing-Hong C Zhan, Stewart S. Taylor
  • Materials classifier, method of using, and method of making
    Patent number: 7537679
    Abstract: The present invention relates to a method of classifying charged molecules such as proteins for quantitative analysis. An analyte solution of the molecules is subjected to separational forces may be fluid drag and electrophoretic force in opposition. The analyte solution may be subjected to a two-phase process. The two-phase process may add both electrophoretic force based upon molecule charge, and differential mobility resistance based upon molecule mass and/or size.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Scott S. Sibbett
  • Method, apparatus, and system for improved erase operation in flash memory
    Patent number: 7539066
    Abstract: Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells between the first memory cell and the second memory cell has a second voltage. Some embodiments include erase verifying only the first memory cell and second memory cell in a first erase verify operation, and erase verifying the plurality of intermediate memory cells in a second erase verify operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Seiichi Aritome
  • Channel selection for mesh networks having nodes with multiple radios
    Patent number: 7539151
    Abstract: Channels are selected for nodes in a wireless mesh network in a mananer that enhances connectivity and throughput in the network. For a node in the network, channel configurations are first identified that satisfy a predetermined connectivity constraint with respect to neighbor nodes of the node. A channel configuration is then selected from the identified configurations based on an achievable throughput of the configuration.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Mustafa Demirhan, Mousumi Hazra, W. Steven Conner
  • Forming compliant contact pads for semiconductor packages
    Patent number: 7538019
    Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
  • Distributed memory initialization and test methods and apparatus
    Patent number: 7539909
    Abstract: A memory system includes multiple memory modules, which communicate with a memory controller over one or more channels. When a memory module receives an initialization command from a processor or the memory controller, the memory module performs an initialization procedure of the memory locations associated with the memory module. In an embodiment, at least a portion of the initialization procedure is performed in parallel with the other memory modules performing initialization procedures. Each memory module may include a buffer module, which receives the initialization command, and generates and sends data packets with the initialization data to the memory locations. A memory module also can receive a test command from the processor or memory controller, which causes the memory module to read data from the memory locations, compare that data with expected data, and keep track of any errors that may occur.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Frank E LeClerg, Peter D. Vogt
  • Method and apparatus for identifying mole growth
    Patent number: 7539334
    Abstract: A mole analysis program generates a digital signature for a first mole, based on a digital image of first, second, and third moles. The program may then determine whether the first mole matches a previously imaged mole, based on the digital signature for the first mole and baseline data with baseline signatures for previously imaged moles. In response to determining that the first mole matches a previously imaged mole, the program may automatically determine whether the first mole has changed. In various embodiments, the digital signature may include angle entries for the digital signature and/or distance entries for the first signature. An angle entry may represent an angle between two lines to connect the first mole with the second mole and the third mole. A distance entry may correspond to the distance between the first mole and the second mole. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Bradley W. Corrion
  • Dynamic network security apparatus and methods or network processors
    Patent number: 7540028
    Abstract: Methods and apparatus for loading a security algorithm in a fast path of a network processor are disclosed. In an example method, a network processor generates a statistic associated with a plurality of communication packets received by the network processor, determines a security attack on the network processor is in progress based on the statistic and loads the security algorithm in the fast path of the network processor.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Suhail Ahmed, Erik J. Johnson, Manasi Deval
  • Method, apparatus, and instruction for performing a sign operation that multiplies
    Patent number: 7539714
    Abstract: Method, apparatus, and program means for performing a sign and multiply operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a first source operand multiplied by a sign value of a second source operand. In some embodiments, the first source operand may be overwritten by the result.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Huy V. Nguyen
  • Optical disk presence detection method and apparatus
    Patent number: 7540000
    Abstract: An apparatus, method, and system for an optical disk drive integrating a radio-frequency identification (RFID) reader is disclosed herein.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Wah Yiu Kwong, Hong W. Wong
  • Method for improved high current component interconnections
    Patent number: 7538440
    Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Dudi I. Amir, Damion T. Searls
  • Enhanced virtual renaming scheme and deadlock prevention therefor
    Patent number: 7539850
    Abstract: In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Ronny Ronen, Michael Bekerman
  • Method and apparatus to interleave bits across symbols from different constellations
    Patent number: 7539270
    Abstract: An encoded input bit stream is interleaved across a number of symbols having different bit sizes in a manner that ensures that the bits assigned to each symbol from the bit stream are separated by a minimum separation. In this manner, bits that are adjacent within the bit stream do not get assigned to the same symbol.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Sumeet Sandhu
  • Switching display update properties upon detecting a power management event
    Patent number: 7538762
    Abstract: Systems and methods provide automatic switching of display update properties such as screen resolution, pixel depth, and refresh rate in response to a power management event. The display update property may be decreased when power is switched from AC power to DC power, for example, when the system is unplugged from a wall outlet and is running on battery power.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Terry M. Fletcher, Edward P. Costales
  • Chemiluminescence sensor array
    Patent number: 7537934
    Abstract: Embodiments of the invention relate to integrated chemiluminescence devices and methods for monitoring molecular binding utilizing these devices and methods. These devices and methods can be used, for example, to identify antigen binding to antibodies. The devices include both a chemiluminescence material and a detector integrated together.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Narayan Sundararajan, Tae-Woong Koo
  • Method and system for performing memory clear and pre-fetch for managed runtimes
    Patent number: 7539831
    Abstract: A method for performing memory allocation includes clearing a section in memory in response to an allocation of memory to an object of a thread. The size of the section is larger than a size of the object and smaller than a size of a thread local area associated with the thread.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Mingqiu Sun, Kumar Shiv, Bob Kasten
  • Exchange of information
    Patent number: 7539639
    Abstract: A method, apparatus, and signal-bearing medium for allowing participants to exchange information regarding a program. The program may be a joint-development program in which the participants are participating, and the information may be confidential information regarding the program that belongs to the respective participants.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Ray R. Bellantoni, Krishnan Raghuram, Howard Cooper, Sandeep Kundra
  • Channel assignment based on spatial strategies in a wireless network using adaptive antenna arrays
    Patent number: 7539496
    Abstract: The present invention can improve efficiency in wireless radio networks using spatial division multiple access (SDMA) strategies. One embodiment of the invention includes determining a quality parameter of a user terminal based on a signal received from the user terminal at a base station. One embodiment further includes determining a co-spatial constraint on the user terminal based on the quality parameter, the co-spatial constraint comprising a limitation on the quantity of additional user terminals with which the user terminal can share a conventional communications channel.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Elvino S. Sousa, Athanasios A. Kasapi, Mitchell D. Trott
  • Method for guest operating system integrity validation
    Patent number: 7539986
    Abstract: A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first process. The file system integrity validation occurs independently of booting the host machine.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Steven L. Grobman
  • Reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric
    Patent number: 7539184
    Abstract: A reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric. The reconfigurable interconnect/switch enables network devices, such as network processor units (NPUs) to selectively communicate with other NPUs, media (via a media interface), and switch fabric (via a switch fabric interface), thus providing flexibility in the use of network line cards and the like. Embodiments of the switching/routing scheme may be employed to support network devices having separate media and/or switch fabric interfaces, as well as network devices having selectable media switch fabric (MSF) interfaces that share signal lines.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, Douglas Lee Stahl, David R. Formisano
  • Grounding of magnetic cores
    Patent number: 7538653
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • User configurable wireless antenna module for computing platforms
    Patent number: 7538731
    Abstract: A removable antenna is configured for a computing platform. This configuring, for example, includes; mounting a bracket on the computing platform designed to accommodate a removable antenna and a removable signal compatible dome. The removable antenna is mounted on the bracket, and the removable signal compatible dome, configured at least in part on the removable antenna, is also mounted on the bracket.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Hong W. Wong, Wah Yiu Kwong
  • BIST to provide phase interpolator data and associated methods of operation
    Patent number: 7539916
    Abstract: In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to under-sample the PI output clock signal from the signal source. In a method of operation, a PI output clock signal is generated in an integrated circuit, and the PI output clock signal is under-sampled in a test latch in the integrated circuit triggered by a test clock signal. Output data from the test latch is transmitted to a test device that is separated from the integrated circuit.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Ofir Kanter, Eran Peleg, Yesayahu Levy
  • System, method and apparatus of protecting a wireless transmission
    Patent number: 7539930
    Abstract: Embodiments of the present invention provide a method, apparatus and system of protecting a wireless transmission. The method according to some demonstrative embodiments of the invention may include based on one or more burst-related sub-commands of a transmit command corresponding to a current packet to be transmitted during a burst period, applying a protection scheme to one or more subsequent packets of the burst period. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Boris Ginzburg, Solomon B. Trainin
  • Removing dry film resist residues using hydrolyzable membranes
    Patent number: 7538021
    Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Houssam Jomaa, Omar Bchir
  • Interpolation in channel state feedback
    Patent number: 7539253
    Abstract: Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations, vector quantization using codebooks, and down-sampling in the frequency domain. A column of a beamforming matrix is quantized using a codebook, a Householder reflection is performed on the beamforming matrix to reduce the dimensionality of the beamforming matrix, and the quantizing and performing of Householder reflection on the previously dimensionality reduced beamforming matrix is recursively repeated to obtain a further reduction of dimensionality of the beamforming matrix. These actions are performed for a subset of orthogonal frequency divisional multiplexing (OFDM) carriers, and quantized column vectors for the subset of OFDM carriers are transmitted.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Qinghua Li, Xintian E. Lin
  • Multi-layer piezoelectric actuators with conductive polymer electrodes
    Patent number: 7538476
    Abstract: A multi-layer piezoelectric actuator with conductive polymer electrodes is described. The piezoelectric actuator comprises a stack of alternating conductive electrode layers and piezoelectric layers. The conductive electrode layers are comprised of a polymeric electrically conductive material. A device for cooling by forced-air convection may comprise the piezoelectric actuator, a fan blade and an alternating current supply. The piezoelectric actuator coupled with the fan blade and the alternating current supply, which is provided for vibrating the fan blade. A method of cooling by forced-air convection comprises supplying an alternating current to the piezoelectric actuator, wherein the alternating current has a frequency and causes the fan blade to vibrate with the same frequency.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Ioan Sauciuc
  • Subcarrier puncturing in communication systems
    Patent number: 7539123
    Abstract: A circuit and method provides subcarrier puncturing by placing no information in subcarriers that suffer from channel impairments where they cannot deliver information. If no energy is placed in these subcarriers, then the transmitted power may be re-allocated to the information carrying subcarriers to increase the Signal-to-Noise Ratio (SNR) at the target node. Or, energy may be place in subcarriers that suffer from channel impairments, but the PAPR of the OFDM symbol may be reduced.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventor: Valentine J. Rhodes
  • Selective bit line precharging in non volatile memory
    Patent number: 7539059
    Abstract: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: June Lee, Daniel Elmhurst
  • Method and Apparatus for the Provision of Unified Systems and Network Management of Aggregates of Separate Systems
    Publication number: 20090132809
    Abstract: A method and apparatus for the provision of unified systems and network management of aggregates of separate systems is described herein.
    Type: Application
    Filed: January 27, 2009
    Publication date: May 21, 2009
    Applicant: Intel Corporation
    Inventors: Mikael Sylvest, Bent Kuhre
  • UNWIND INFORMATION FOR OPTIMIZED PROGRAMS
    Publication number: 20090133008
    Abstract: Analyzing a first binary version of a program and unwind information associated with the first binary version of the program, performing optimization on the first binary version of the program to produce a second binary version of the program based at least in part on the results of the analysis, and generating new unwind information for the second binary version of the program based at least in part on the results of the analysis and at least in part on the optimization performed.
    Type: Application
    Filed: January 16, 2009
    Publication date: May 21, 2009
    Applicant: INTEL CORPORATION
    Inventors: Harish G. Patil, Robert Muth, Geoff Lowney
  • Micro-chimney and thermosiphon die-level cooling
    Publication number: 20090129022
    Abstract: A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 21, 2009
    Applicant: INTEL CORPORATION
    Inventors: Gregory M. Chrysler, James G. Maveety
  • REDUCING DEFECTS IN SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURES
    Publication number: 20090127541
    Abstract: Reducing defects in semiconductor quantum well structures is generally described. In one example, an apparatus includes a semiconductor substrate including silicon, a buffer film epitaxially grown on the semiconductor substrate, the buffer film comprising silicon, germanium, and an impurity, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film and wherein the impurity disrupts lattice structure dislocation gliding in at least the first semiconductor film.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Applicant: INTEL CORPORATION
    Inventors: Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
  • Sintered metallic thermal interface materials for microelectronic cooling assemblies
    Patent number: 7535099
    Abstract: A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Chi-won Hwang
  • General input/output architecture, protocol and related methods to implement flow control
    Patent number: 7536473
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Packet classification
    Patent number: 7535899
    Abstract: An apparatus and method includes grouping filters to form a tree according to a bitmask. The bitmask includes entries indicating whether a value is assigned to an element of a filter. The method also includes receiving a packet that includes a particular bitmask, searching the tree to determine filters associated with the particular bitmask and the associated values, and returning a set of filters that are an intersection of the filters indicated by the associated values.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Pankaj N. Parmar, David M. Durham
  • Processor having inactive state of operation and method thereof
    Patent number: 7536485
    Abstract: Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Gila Kamhi, Zelig Wayner, Amit Gradstein, Yoad Yagil, Thierry Pons, Ittai Anati, Ranan Fraer
  • Audio-based attention grabber for imaging devices
    Patent number: 7535496
    Abstract: A digital imaging device such as a digital camera or a video camera may include the capability to store audio files. These audio files may be generated under user control when the user wishes to take a picture or capture video. The audio files may be played back as attention grabbers to attract the attention of the imaging subjects. After attracting the attention of the subjects by playing back a recorded audio sound, an image may be automatically captured.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventor: Lenka M. Jelinek
  • Thread-based engine cache partitioning
    Patent number: 7536692
    Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Wilson Y. Liao, Prashant R. Chandra, Jeen-Yuan Miin, Yim Pun
  • Aligned nanotube bearing composite material
    Patent number: 7534648
    Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Ravindra Tanikella
  • Built-in self test for memory interconnect testing
    Patent number: 7536267
    Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: David Zimmerman, Jay J. Nejedlo
  • Carbon-carbon and/or metal-carbon fiber composite heat spreader
    Patent number: 7534650
    Abstract: A heat spreader, comprised of a plurality of carbon fibers oriented in a plurality of directions, with a carbon or metal matrix material dispersed about the fibers, is described. The carbon fibers facilitate the spreading of heat away from the smaller semiconductor device and up to a larger heat removal device, such as a heat sink.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Sabina J. Houle, Paul A. Koning, Greg M. Chrysler
  • Packaging method for circuit board
    Patent number: 7533457
    Abstract: A method includes populating a circuit board with components, and encapsulating the circuit board and the components with a material. The method further includes separating the circuit board into a plurality of separate devices.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Richard B Foehringer, Jason E Snodgress, Steven R. Eskildsen, John G. Meyers
  • Thermoset polyimides for microelectronic applications
    Patent number: 7534649
    Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Stephen E. Lehman, Jr., James C. Matayabas, Jr., Saikumar Jayaraman
  • Method and apparatus to communicate graphics overlay information to display modules
    Patent number: 7535478
    Abstract: A method and apparatus to communicate graphics information are described.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Randy R. Dunton, Eric Auzas, Nicholas J. Stasik
  • Method to correct EUVL mask substrate non-flatness
    Patent number: 7534532
    Abstract: Methods to correct a non-flatness of a mask substrate are described. At least a pair of correction layers are formed on the substrate over a non-flat region of a front surface of a substrate. A thickness of the at least the pair of the correction layers is determined by a peak-to-valley distance of the non-flat region of the substrate. A portion of the correction layers over the non-flat region is heated locally. Heating changes the thickness of the portion of the correction layers and removes the non-flat region from a top surface of the correction layers without physically removing any materials. At least the pair of the correction layers is formed on a back surface of the substrate to compensate for a stress induced by the correction layers on the front surface of the substrate.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventor: Pei-Yang Yan
  • Apparatus and method of block acknowledgements with reduced recipient state information
    Patent number: 7535858
    Abstract: An apparatus and method for block acknowledgements with reduced recipient state information are described. In one embodiment, the method comprises the storing of a receive state for a block of frames received during a transmission opportunity (TXOP) with an on-chip state memory. Once stored, an immediate block acknowledgement, including the receive state information, may be transmitted to an originator according to a block acknowledgement request (BAR) received during the TXOP. In the embodiments described, the BAR is received during the TXOP in which the block of data frames were transmitted to a recipient. In one embodiment, the recipient is free to discard the receive state information to free space within the on-chip system memory by requiring the originator to maintain the receive state information of blocks of data frames transmitted during TXOPs. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Solomon Trainin, Robert J. Stacey
  • Various methods and apparatuses for a multiple input-voltage-level voltage-regulator and a multiple voltage-level DC power supply
    Patent number: 7535122
    Abstract: A method, apparatus, and system are described in which operating characteristics of voltage regulator (VR) may be controlled. Example operating characteristics that are controlled may be 1) power conversion efficiency based on load demand on the VR, 2) response rate to a transient deviation from a regulated output parameter, such as voltage or current, of the VR based on either 1) measured load or 2) receipt of an indication from a first load communicating that anticipated load conditions may cause the transient deviation from a set point of the regulated output parameter due to a significant change in load demand, or other similar operating characteristic. The VR may select an operating input voltage from two or more input voltages to control the operating characteristics of the VR by receiving a selection signal. Other embodiments are described.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Horacio Visairo-Cruz, Pavan Kumar
  • Methods including fluxless chip attach processes
    Patent number: 7534715
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Susheel Jadhav, Daoqiang Lu, Nitin Deshpande