Abstract: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a bit pattern value at a first memory device from a host device via an interface to establish a first sideband address and the first memory device receiving a unique device identification (ID) from the host device.

Abstract: In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a circuit board having integrated contacts to mate with corresponding pads of a semiconductor device. At least some of the integrated contacts are of varying sizes to enable different contact resistances between the corresponding integrated contacts and pads, enabling reduced loading forces to adapt the semiconductor device to the circuit board. Other embodiments are described and claimed.

Abstract: A planar light wave circuit may be formed with a pair of waveguides arranged in close proximity to one another. At least one of the waveguides may be segmented. Through segmentation, the average mode-field diameter may be adjusted. Controlling the average mode-field diameter enables precise control over the coupling characteristics.

Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress digital images in a lossless or a lossy manner. In some embodiments, a display controller may quantize pels of a digital image and may identify runs of successive quantized pels which are equal. The display controller may generate a symbol to represent an identified run of pels. The symbol may comprise a run length and a quantized pel that may be used to reconstruct the run of pels. The symbol may further comprise an error vector for each of the pels of the run that may be used to further reconstruct the run of pels.

Abstract: A program different than an operation system may be utilized to partially update an original image of system code. In one embodiment, operating system code may be adaptively stored and updated within a non-volatile storage device across at least two different memories into at least two code objects based on the relative utilization of the system code in the two code objects. Operating system patching or application and driver updates may be provided without re-writing an entire image of operating system code in some embodiments. The tuning of operating system code storage may be implemented based on a usage pattern of the operating system code on a device in some cases.

Abstract: A method includes installing a device under test (DUT) into each of a plurality of burn-in boards. The method further includes docking each of the burn-in boards to a respective docking location, each of the burn-in boards with a single respective DUT installed therein. The method further includes subjecting the DUTs to a self-heating burn-in procedure while the burn-in boards are docked to the docking locations. Other embodiments are described and claimed.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register whether there interrupts at a queue manager to be processed by a processor, the processor reading an interrupt status register within the queue manager, the processor processing packets corresponding to addresses stored in each of a plurality of queues within the queue manager, selecting a second of a plurality of programmable interrupt enable registers and the controller determining for the second register whether there interrupts at the queue manager to be processed by the processor.

Abstract: First radicals and second radicals are simultaneous deposited into a space defined by two adjacent lines of photoresists and an underlying layer. A portion of the first radicals and the second radicals combine to form a polymer layer on the layer in the center of the space, and substantially simultaneously, another portion of thee first radicals remove the underlying layer near the base of the photoresists. The first radicals may be fluorine-rich and the second radicals may be carbon-rich.

Abstract: An automatic gain control (AGC) system and method for implementing a wide dynamic range automatic gain control (AGC) are disclosed. The AGC system features a large gain adjustment suitable for integration in silicon tuners. The AGC structure employs a pair of classical current steering stages, architecturally arranged to share the gain back-off characteristic in a novel “ping-pong” arrangement. The AGC system and method deliver a wide dynamic range at low power dissipation in radio frequency (RF) systems, but may be implemented as well in other applications.

Abstract: A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.

Abstract: Generally, this disclosure describes an energy-efficient Ethernet communications approach. In at least one embodiment described herein, an Ethernet controller may be configured to operate in an active power state to transmit or receive data packets at a maximum available link speed. The maximum available link speed may be determined by a negotiation between the Ethernet controller and a link partner coupled to the Ethernet controller. Once the data packets are transmitted or received, the Ethernet controller may be configured to operate in an idle power state to reduce energy consumption.

Abstract: Disclosed is a package having a thin film bulk acoustic resonator (FBAR). The package may be utilized for suppressing spurious resonance occurred during operation of the FBAR. The package includes a negative impedance converter (NIC) operatively coupled to the FBAR through at least one interconnect. The at least one interconnect includes transmission lines and bonding wires. The package further includes a filter operatively coupled to the NIC. The filter exhibits a parallel resonance at a predefined frequency. The parallel resonance exhibited by the filter is converted to a series resonance by the NIC such that the series resonance of the NIC is responsible for suppressing the spurious resonance occurring during the operation of the FBAR.

Abstract: A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache.

Abstract: A direct conversion receiver and a method for correcting phase imbalance therein is disclosed. An input signal is applied to an in-phase channel and a quadrature channel of the receiver. The input signal is processed by the direct conversion receiver to obtain an in-phase zero intermediate frequency (IF) signal in the in-phase channel and a quadrature zero-IF signal in the quadrature channel. The in-phase zero-IF signal and the quadrature zero-IF signal are filtered to obtain a fixed band signal. A phase imbalance correction value is obtained for the fixed-band quadrature zero-IF signal as a function of the frequency of the fixed-band in-phase zero-IF signal and the fixed-band quadrature zero-IF signal. The in-phase zero-IF signal and the quadrature zero-IF signal are sampled and the phase imbalance correction value is applied using an interpolation to the sampled quadrature zero-IF signal or to the sampled in-phase zero-IF signal to correct the phase imbalance in the direct conversion receiver.

Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Abstract: A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Abstract: The present invention includes various embodiments of a method and apparatus for increasing the networking capacity of existing wireless networks by using robust header compression. In one embodiment, the invention is a method. The method includes initiating a link within a wireless computer network. The method further includes transmitting data through the link using robust headers. The method may also include negotiating parameters of the link. In an alternate embodiment, the invention is also a method. The method includes receiving a request for a link within a wireless computer network. The method also includes receiving data through the link using robust headers. The method may further include negotiating parameters of the link. In another alternate embodiment, the invention is also a method. The method includes initiating a link within a wireless computer network.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.

Abstract: An architecture for a receiver of a wireless device having a Low Noise Amplifier (LNA) transconductor to receive a signal from an antenna, a mixer meshed with the LNA transconductor, and an amplifier/filter meshed with the mixer to provide a baseband output signal.

Abstract: In some embodiments, the invention involves a system and method relating to software caching with bounded-error delayed updates. Embodiments of the present invention describe a delayed-update software-controlled cache, which may be used to reduce memory access latencies and improve throughput for domain specific applications that are tolerant of errors caused by delayed updates of cached values. In at least one embodiment of the present invention, software caching may be implemented by using a compiler to automatically generate caching code in application programs that must access and/or update memory. Cache is accessed for a period of time, even if global data has been updated, to delay costly memory accesses. Other embodiments are described and claimed.

Abstract: A personal computer includes a PBX control program and one or more switch cards located in expansion board slots. The one or more switch cards are coupled to one or more port expansion units (PEU), which are coupled to telecommunication lines out to the various extension phones at the customer premises. Each PEU contains its own digital signal processor (DSP) so that distributed digital signal processing may be implemented to avoid any bottlenecks. One master PEU is coupled to a switch card by a time division multiplexed (TDMA) bus as well as a packet switched control bus, and all the other PEUs, if any, are coupled to the master PEU by extensions of the TDMA and packet switched buses. The TDMA bus carries PBX real time conversations while the packet switched bus carries control information, voicemail outbound message data packets, and inbound voicemail data packets.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.

Abstract: According to some embodiments, a Single-Instruction/Multiple-Data (SIMD) averaging instruction is used to process pixels of image data. The averaging instruction generates a set of four-pixel averages, where each average is generated from two pixels in a first source register and two pixels in a second source register. The first source register contains a plurality of pixels from a first row of pixels and the second source register contains a plurality of pixels from a second row. In one embodiment, the first and second rows are adjacent rows in an image and the averaging instruction is used, for example, to down-scale an image, perform color conversion, and the like. In another embodiment, the first and second rows are from different images and the averaging instruction is used, for example, in motion estimation for video encoding, in motion compensation for video decoding, and the like.

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.

Abstract: Provided are a method, system and program for effecting an operating system mode change from one mode to another. In one embodiment, the operating system in one mode is placed in a sleep state in which volatile memory remains active. In booting an operating system from the sleep state, a flag may be detected indicating an operating system mode transfer request. In response, contents of a selected range of volatile memory allocated to the first operating system mode may be swapped with the contents of a selected range of a reserve portion of volatile memory allocated to the second operating system mode. Booting of an operating system in the second mode may be completed using the swapped contents of the volatile memory. Additional embodiments are described and claimed.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad; an anode connected electrically to the wafer carrier; and a power supply connected to the anode and the cathode. The present invention further discloses a method to remove a surface layer from a wafer using a polishing pad, a slurry, and an electrical current.

Abstract: An interleaver and scheme for interleaving in which highly correlated bits are maximally separated. The scheme involves interleaving a set of bits to be delivered to a modulation system that utilizes a quantity of N carrier frequencies. A first block of N consecutive bits is assigned to each of N bins, on a one-bit-per-one-bin basis. The aforementioned assignment proceeds in a particular sequence. A second block of N consecutive bits is assigned to each of the N bins, on a one-bit-per-one-bin basis. The second block is assigned in the same sequence the first block was assigned. The second block is consecutive to the first block.

Abstract: Adapting a wireless communications link between a transmitter and a receiver involves reducing the RF bandwidth of an uplink communications channel to achieve a desired channel quality. The RF bandwidth of the uplink communications channel is reduced when the desired channel quality is not achieved using the entire available RF bandwidth for uplink communications. Reducing the RF bandwidth of an uplink channel enables the uplink limit of a subscriber unit to be extended beyond what is possible when the entire available RF bandwidth is used for uplink communications. Additional uplink time slots can be allocated to the uplink communications channel with the reduced RF band so that a constant overall transmission rate can be maintained between the transmitter and the receiver.

Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.

Abstract: Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to the power saving message. In one embodiment, the power saving message is issued by de-asserting a bus arbitration signal and the power saving activity can include disabling one or more input buffers of the controller.

Abstract: A small water-cooling type electronic component cooling apparatus is provided. The electronic component cooling apparatus comprises a so-called water-cooling heat sink 3, a radiator 7 cooled by an electric fan 5, first and second coolant paths 9, 11 for circulating a coolant between the heat sink 3 and the radiator 7, and an electric pump 13 to supply a moving energy to the coolant. The electric pump 13 is arranged at a position facing the heat-radiating portion of the radiator 7.

Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

Abstract: Disclosed is a method for reducing number of bits in a Media Access Protocol (MAP) message. The MAP message comprises a plurality of information elements grouped into one of a first set of information elements and a second set of information elements. The first set of information elements are arranged in a pre-defined order and each of the second set of information elements is inserted into one of a prefix position to the pre-defined order, a suffix position to the pre-defined order and an intermediate position in-between two information elements in the pre-defined order. Each information element of the second set of information elements is then coded based on position of the information element relative to the position of the first set of information elements in the pre-defined order, thereby reducing the number of bits in the MAP message.

Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

Abstract: An electronic system of an Integrated circuit (IC) for conditioning and identification of bad blocks in the IC is disclosed. The electronic system includes at least one cyclic scan chain and at least one multiplexer. A cyclic scan chain includes a plurality of flip-flops, which are connected in a cascaded manner. A multiplexer is connected between two adjacent flip-flops of the cyclic shift register. The multiplexer has a first input pin connected to output of a first flip-flop, a second input pin connected to a user pin and an output pin connected to an input of a second flip-flop. The multiplexer is configured to condition the plurality of flip-flops through the user pin by programming logic bits in the plurality of flip-flop. The output of the first flip-flop is configured to read the logic bits in the plurality of flip-flops to identify a bad block in the IC.

Abstract: Disclosed is a socket assembly for electrically engaging an Integrated Circuit (IC) package with a printed circuit board. The socket assembly includes a socket body and a Pick-and-Place (PnP) cap. The socket body is mounted on the printed circuit board. Further, the PnP cap is capable of detachably mounting on the socket body. An upper surface of the PnP cap includes a raised portion with multiple chamfered portions projecting out from the raised portion. The multiple chamfered portions enable easier detachment of the PnP cap from the socket body.

Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.

Abstract: A computer system may include a keyboard housing that is capable of being moved at least partially into or out of a chassis. The chassis is associated with a transducer and an air chamber. Movement of the keyboard housing may cause size of the air chamber to be adjusted. When the size of the air chamber is increased, the transducer becomes more sensitive to sound in lower frequency ranges.

Abstract: A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.

Abstract: Described are a system and method of transmitting a time slot status message between nodes in a SONET network. One or more time slots in a SONET link may be allocated to provision a SONET circuit. Upon provisioning or de-provisioning the SONET circuit, a time slot status message may be transmitted to one or more non-participating nodes in the SONET network to indicate a change in status of one or more time slots of the SONET link.