Patents Examined by A. Au
  • Patent number: 10964284
    Abstract: An electronic component board includes a signal line area in which signal lines extend in parallel to each other and a frame area that surrounds the signal line area. In the frame area, terminals, connection lines that connect the signal lines and the terminals, and circuits that are arranged along a portion of an outline of the signal line area and on respective line paths of the connection lines. The connection lines are routed such that an entire outline thereof is formed in a fan shape so as to be narrowed from the signal lines toward the terminals. The circuits include a first circuit and a second circuit. The second circuit has a small X-dimension in an arrangement direction of the circuits and a large Y-dimension in a perpendicular direction.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 30, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10957880
    Abstract: An electro-optical panel includes: an electro-optical element emitting a light or adjusting a transmittance of a light; and a stretch film including a polymeric material, wherein a main stretching axis direction of the stretch film is disposed within a range of ±30° with respect to a side of the electro-optical panel.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 23, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Harumi Okuno, Osamu Sato
  • Patent number: 10955957
    Abstract: An electronic device is provided. The electronic device may include a display including a front surface area and a side surface area disposed in at least one side of the front surface area, a first sensor included under the side surface area and configured to sense pressure applied to the side surface area; and a processor operatively connected with the display and the first sensor. The processor may be configured to determine a position of at least one point of the side surface area corresponding to the sensed pressure, if the sensed pressure using the first sensor is within a first specified range, and to display at least one graphic object on an area corresponding to the determined position.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Sung Lee, Na Young Kim, Ha Rim Kim, Na Kyoung Lee, Hyun Soo Kim, Dong Hyun Yeom, Chang Ryong Heo
  • Patent number: 10957777
    Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Seminconductor Manufacturing Company Limite
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10949028
    Abstract: A texture recognition method, a texture recognition device, and a display device. The texture recognition method includes: receiving a texture recognition signal by using a light blocking structure having a light transmission aperture; performing an amplification process on the texture recognition signal to obtain an amplified texture recognition signal; and detecting a valley line and a ridge line in a texture based on the amplified texture recognition signal.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaoquan Hai, Haisheng Wang, Jian Gao
  • Patent number: 10950611
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 10943998
    Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: March 9, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao
  • Patent number: 10942444
    Abstract: Optical control modules for integrated circuit device patterning and reticles and methods including the same. The methods include exposing, via a reticle, initial and subsequent reticle exposure fields on a surface of a semiconductor substrate. The initial and subsequent reticle exposure fields pattern corresponding array regions and margin regions on the semiconductor substrate. The initial and subsequent reticle exposure fields partially overlap such that an initial optical control module (OCM), which is patterned during exposure of the initial reticle exposure field, and a subsequent OCM, which is patterned during exposure of the subsequent reticle exposure field, both are positioned within a single control module die. The reticles include reticles that can be utilized during the methods or that can form the integrated circuit devices. The integrated circuit devices include integrated circuit devices formed utilizing the methods or the reticles.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Leendertjan Mekking, Johannes Cobussen, Antonius Hendrikus Jozef Kamphuis
  • Patent number: 10943911
    Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • Patent number: 10930525
    Abstract: A carrier substrate includes a core layer and at least one unit pattern portion, and the unit pattern portion includes a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, a second metal layer disposed on the release layer, and a third metal layer disposed on the second metal layer and covering side surfaces of the release layer, and a method of manufacturing a semiconductor package using the carrier substrate.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yieok Kwon, Ikjun Choi
  • Patent number: 10930818
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; and a current blocking (CB) layer disposed on the first surface; a transparent conductive layer disposed on or above the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a sidewall of the CB layer comprises a first surface section and a second surface section having different slopes.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 23, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
  • Patent number: 10921901
    Abstract: A multi-functional human interface device includes a control unit and a first multi-functional input button. The first multi-functional input button includes a cover unit configured to receive a touch input of a user's finger, an electrode unit including a transmitter and a receiver to form an electric field, an elastic unit configured to move from a first height to a second height when a first pressure is applied from the cover unit and configured to move back to the first height when the first pressure from the cover unit is released, and a switch unit configured to generate an electric signal representing an input of a predetermined letter.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 16, 2021
    Assignee: INNOPRESSO, INC.
    Inventor: Eunhyung Cho
  • Patent number: 10921902
    Abstract: A multi-functional human interface device includes a control unit and a first multi-functional input button. The first multi-functional input button includes a cover unit configured to receive a touch input of a user's finger, an electrode unit including a transmitter and a receiver to form an electric field, an elastic unit configured to move from a first height to a second height when a first pressure is applied from the cover unit and configured to move back to the first height when the first pressure from the cover unit is released, and a switch unit configured to generate an electric signal representing an input of a predetermined letter.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 16, 2021
    Assignee: INNOPRESSO, INC.
    Inventor: Eunhyung Cho
  • Patent number: 10923025
    Abstract: A method for compensating the pixel driving circuit may include: in a light emitting phase of the pixel driving circuit, sensing an electric signal of the first electrode of the electroluminescent element, and calculating an electrical compensation signal based on the electric signal; in the light emitting phase of the pixel driving circuit, sensing a brightness signal of the electroluminescent element by a photosensitive sensor and calculating an optical compensation signal according to the brightness signal; and generating a comprehensive compensation signal according to the electrical compensation signal and the optical compensation signal, and controlling a signal on a control terminal of the drive transistor according to the comprehensive compensation signal.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: February 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cuili Gai, Yicheng Lin, Ling Wang, Pan Xu
  • Patent number: 10923621
    Abstract: The present invention uses a photolithography process and an electroplating process to perform. TAV copper filling and patterning of the fabrication of the double side copper-plated layers to plate the double side copper-plated layers in advance at the TAV through holes to serve as a stress buffer layer of the aluminum nitride substrates. Then the subsequent pattern designs of the copper-plated layers are customized. According to the simulation theory calculations, it is proved that the stress which accumulates on the short-side of the copper-plated layer of the aluminum nitride substrate with the asymmetric structure may be effectively reduced to facilitate the improvement of the reliability of the aluminum nitride substrate.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 16, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chun-Te Wu, Yang-Kuo Kuo, Cheng-Hung Shih, Hong-Ting Huang
  • Patent number: 10910259
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignees: TOKYO ELECTRON LIMITED, IMEC VZW
    Inventors: Koichi Yatsuda, Tatsuya Yamaguchi, Yannick Feurprier, Frederic Lazzarino, Jean-Francois de Marneffe, Khashayar Babaei Gavan
  • Patent number: 10910272
    Abstract: A support substrate including a plurality of channels on a front side is provided. A cover layer is formed by anisotropically depositing a sacrificial cover material over the plurality of channels. Cavities laterally extend within the plurality of channels underneath a horizontally extending portion of the cover layer. An encapsulation layer is conformally deposited. First semiconductor devices, first metal interconnect structures, and first bonding pads are formed over a top surface of the encapsulation layer. A device substrate with second bonding pads is provided. The second bonding pads are bonded with the first bonding pads to form a bonded assembly. Peripheral portions of the encapsulation layer are removes and peripheral portions of the cover layer are physically exposed. The cover layer is removed employing an isotropic etch process by propagating an isotropic etchant through the cavities to separate the support substrate from the bonded assembly.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Senaka Kanakamedala, Raghuveer S Makala
  • Patent number: 10910515
    Abstract: A method of manufacturing a light-emitting device includes providing a package having an upper surface and defining a recess, the recess having an opening at the upper surface. A light-emitting element is placed on a bottom surface of the recess of the package, and the recess of the package is filled with an uncured sealing member containing a silicone resin. The package is held in a liquid in a state in which the uncured sealing member is filled in the recess of the package, and the uncured sealing member is cured by heating the package in which the uncured sealing member is filled in the recess.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: February 2, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Chinami Nakai
  • Patent number: 10901152
    Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 26, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 10896846
    Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Patlolla, Cornelius Brown Peethala, Chih-Chao Yang