Patents Examined by A. Au
  • Patent number: 10319322
    Abstract: The present invention providing a gate driver used in display panel, wherein comprises: a chamfering module is configured to receive gate turn-on voltage signals and square wave controlling signals, and chamfers the gate turn-on voltage signals in accordance with the square wave controlling signals to generate and output chamfered gate turn-on voltage signals; and a level shifting module is configured to receive the chamfered gate turn-on voltage signals, inputs voltage signals and gate cut-off voltage signals, and outputs the chamfered gate turn-on voltage signals or the gate cut-off voltage signals in accordance with a voltage value of the input voltage signal. By integrating a chamfering module and a digital adjustable resistance module into a gate driver, it is not necessary to provide a chamfering circuit on a CB of display panel, so as the CB can be miniaturized.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Zhao Wang
  • Patent number: 10312435
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A hard mask material is deposited over a magnetic memory element material, and a chemical template layer such as brush or mat material is deposited over the hard mask. A mask structure is formed over the soluble polymer. The mask structure is configured with openings having a center to center spacing that is an integer multiple of a block copolymer material. The openings in the mask structure can be shrunk by depositing a spacer material. The chemical template layer is chemically patterned, such as by a quick plasma exposure and the mask is removed. A block copolymer material is then deposited over the chemical template and annealed to form block copolymer cylinders that are located over the patterned portions of the chemical template and between the patterned portions.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 4, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava
  • Patent number: 10304991
    Abstract: The present invention provides a chip mounting system and a method for mounting chips. The chip mounting system includes a first carrier device, a second carrier device, and a chip capturing device. The first carrier device includes a plurality of first carrier platforms for respectively carrying a plurality of semiconductor structures. Each semiconductor structure includes a base layer and a plurality of light emitting chips disposed on the base layer. The second carrier device includes a second carrier platform for carrying a circuit substrate. The chip capturing device is used for moving the light emitting chip from the base layer to the circuit substrate. The red, the green, and the blue light-emitting groups of the same sequence are disposed adjacent to each other, so that the red, the green, and the blue light-emitting chips of the same sequence are arranged adjacent to each other to form a pixel.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: May 28, 2019
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 10304730
    Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 10297660
    Abstract: A semiconductor device includes: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having an impurity concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; an accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having an impurity concentration higher than the drift region; and a plurality of trench sections provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate and provided with a conductive section therein. A length of the accumulation region in a depth direction of the semiconductor substrate is less than 1.5 ?m.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10297203
    Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; a leakage prevention circuit to preform a process to the leakage of the input circuit; an output circuit to generate a scanning driving signal and output to the level scanning line to drive a pixel unit.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yafeng Li
  • Patent number: 10290693
    Abstract: Provided is a novel display panel that is highly convenient or reliable or a display panel with a high pixel aperture ratio. The display panel includes the first display element, the first conductive film electrically connected to the first display element, the second conductive film having a region overlapping with the first conductive film, the second insulating film having a region sandwiched between the second conductive film and the first conductive film, a pixel circuit electrically connected to the second conductive film, and the second display element electrically connected to the pixel circuit. The second insulating film includes an opening, and the second conductive film is electrically connected to the first conductive film in the opening.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Kusunoki
  • Patent number: 10290580
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Wei Liu, Tai-I Yang, Cheng-Chi Chuang, Tien-Lu Lin
  • Patent number: 10283045
    Abstract: A display device including a light emitting element, a drive transistor connected to the light emitting element, a first switching element connected to the drive transistor and a main power supply line, a second switching element connected to the drive transistor and a reset power supply line, a third switching element connected to the drive transistor and a signal line, a fourth switching element connected to the third switching element and an initialization power supply line, and a capacitor element connected to the drive transistor and the third switching element, wherein two horizontal periods ON signal is supplied to a gate terminal of each of the second switching element, third switching element and fourth switching element respectively.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 7, 2019
    Assignee: Japan Display Inc.
    Inventors: Makoto Shibusawa, Hiroyuki Kimura, Tetsuo Morita
  • Patent number: 10282032
    Abstract: A display device according to an embodiment includes a display panel, a touch module located on the display panel, a cover film located on the touch module, a first adhesive layer located between the display panel and the touch module, and a second adhesive layer located between the touch module and the cover film, wherein a thickness ratio of the first adhesive layer and the second adhesive layer with respect to a thickness of the display device is in a range of 7% to 40%.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 7, 2019
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: In Kyu Song, Hee Bong Kim, Jun Hee Sung, Min-Ho Lim
  • Patent number: 10283512
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 10273143
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 10269792
    Abstract: A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Yu, Shao-Ming Yu
  • Patent number: 10269624
    Abstract: An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xi-Zong Chen, Y. H. Kuo, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10269847
    Abstract: A method of forming a microlens may include using two layers of photoresist. The first photoresist layer may be patterned to form a first portion of a pixel microlens. A second photoresist layer may be patterned on top of the first portion of the pixel microlens. The second photoresist may then be melted so that the second photoresist layer has a curved upper surface. The first and second photoresist layers may combine to form the pixel microlens. The indices of refraction of the first and second photoresist layers may the same or different. The melting point of the second photoresist may be lower than the melting point of the first photoresist.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Christopher Parks
  • Patent number: 10262612
    Abstract: The present disclosure provides a scan compensation method and a scan compensation circuit of a gate driver. The scan compensation method comprises: when the gate driver switching from first scanning mode to second scanning mode or from second scanning mode to first scanning mode, performing a first operation to a clock signal and a first compensation signal of the gate driver, and performing a second operation to the obtained signals and a second compensation signal, wherein the first scanning mode is a sequential scan mode, the second scanning mode is non-sequential scan mode.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 16, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Zhao Wang
  • Patent number: 10262611
    Abstract: The present disclosure illustrates a display device. The displaying device comprises a display panel, at least one scan driving unit and a data driving unit. The display panel is divided into display regions respectively having pixel sets. At least one scan driving unit having scanning lines couples to the pixel sets. The at least one scan driving unit outputs scanning signals to corresponding display regions upon receiving a first control signal. The data driving unit outputs data signals to the corresponding display regions upon receiving a second control signal. In response to respectively receiving the first or second control signals, the scan driving unit outputs the scanning signals or the data driving unit outputs the data signals to the corresponding display regions, so as to simultaneously scan the display regions respectively having the pixel sets in sequence with corresponding scanning patterns.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 16, 2019
    Assignee: SILICON TOUCH TECHNOLOGY INC.
    Inventors: Kuei-Jyun Chen, Tao-Lun Darren Chin
  • Patent number: 10256138
    Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Sorin Stefanescu, Joseph R. VanDeWeert
  • Patent number: 10256348
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Kazuya Hanaoka, Shinya Sasagawa, Satoru Okamoto
  • Patent number: 10249728
    Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Andre Labonte, Ruilong Xie, Lars Liebmann, Nigel Cave, Guillaume Bouche