Abstract: A display device includes a substrate including a first area, a display area surrounding the first area, and a peripheral area surrounding the display area and including a bent area; a display unit including pixels; a driving circuit in the peripheral area; and a fan-out unit in the peripheral area and including a first wiring portion and a second wiring portion apart from each other in the bent area. The first wiring portion includes first wirings. Each of the first wirings includes a first portion extending in a first direction between the display unit and the bent area, and a second portion extending in a second direction. A width of the first portion is greater than a width of the second portion.

Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Abstract: A method for providing haptic feedback includes sensing a user's input through a display panel, determining haptic feedback corresponding to the input, and controlling a voltage applied to each of the plurality of actuators to provide the determined haptic feedback to a location where the input is sensed, wherein the controlling of the voltage applied to each of the plurality of actuators includes adjusting the voltage applied to each of the plurality of actuators to reduce the magnitude of radiation noise of the panel due to excitation of the plurality of actuators and to uniformize the magnitude of the noise for each location of the panel.

Abstract: A method of manufacturing a semiconductor structure includes steps of providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer over the second substrate, and a second conductive pad surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; forming a first opening extending through the second substrate and partially through the second dielectric layer; disposing a dielectric liner conformal to the first opening; forming a second opening extending through the second dielectric layer and the second conductive pad to at least partially expose the first conductive pad; and disposing a conductive material within the first opening and the second opening to form a conductive via over the first conductive pad.

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

Abstract: An apparatus for delivering alternate user input between an alternate input device and an output device, the output device configured to receive input from a conventional input device, the output device not configured to receive input from the alternate input device, the apparatus including an input interconversion processor that receives the alternate user input from the alternate input device, a processing pipeline that converts the alternate user input to a conventional user input of a type normally received by the output device from the conventional input device, and an output port that transmits the conventional user input.

Abstract: Electromechanical polymer (EMP) actuators are used to create haptic effects on a user interface deface, such as a keyboard. The keys of the keyboard may be embossed in a top layer to provide better key definition and to house the EMP actuator. Specifically, an EMP actuator is housed inside an embossed graphic layer that covers a key of the keyboard. Such a keyboard has a significant user interface value. For example, the embossed key provides the tactile effect of the presence of a key with edges, while allowing for the localized control of haptic vibrations. For such applications, an EMP transducer provides high strains, vibrations or both under control of an electric field. Furthermore, the EMP transducer can generate strong vibrations. When the frequency of the vibrations falls within the acoustic range, the EMP transducer can generate audible sound, thereby functioning as an audio speaker.

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via.

Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

Abstract: A display device includes a first transistor including a first channel region, a first gate electrode overlapping the first channel region, and a first electrode connected to a node receiving a driving voltage, a second transistor electrically connected to the first electrode of the first transistor, the second transistor including a second channel region and a second gate electrode overlapping the first channel region and receiving a scan signal, a light emitting element electrically connected to a second electrode of the first transistor, a first conductive line overlapping the first gate electrode with the first channel region in between and receiving a variable voltage different from the driving voltage, and a second conductive line overlapping the second gate electrode with the second channel region in between and receiving the scan signal.

Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A driver circuit has first and second switching drivers for driving the transducer in a bridge-tied-load configuration, each of the switching drivers having a respective output stage for controllably switching the respective driver output node between high and low switching voltages with a controlled duty cycle. Each of switching drivers is operable in a plurality of different driver modes, wherein the switching voltages are different in said different driver modes. A controller controls the driver mode of operation and the duty cycle of the switching drivers based on the input signal. The controller is configured to control the duty cycles of the first and second switching drivers within defined minimum and maximum limits of duty cycles; and to transition between driver modes of operation when the duty cycle of one of the switching drivers reaches a duty cycle limit.

Abstract: A display device includes a display panel, a memory, a dithering processor, and a panel driver. The display panel includes a display surface, and the memory stores dither patterns with respect to at least one spot area included in the display surface. The dithering processor selects a dither pattern among the dither patterns in a predetermined time unit and outputs a compensation image signal corresponding to the dither pattern. The panel driver outputs a data signal corresponding to the spot area based on the compensation image signal. Each of the dither patterns includes a first grayscale area having a first grayscale value higher than a first target grayscale value of the spot area and a second grayscale area having a second grayscale value lower than the first target grayscale value.

Abstract: A light emitting device and a light emitting method are provided. The light emitting device includes a plurality of sub-pixels. Each of the sub-pixels displays a grayscale during a frame. The frame includes N sub-frames. Each of the sub-frames include a scan period and an emission period. Each of the sub-pixels include a pixel circuit and a light emitter. The pixel circuit include a current control circuit and a pulse width modulation (PWM) circuit. The current control circuit receives an analog signal, and outputs a driving current according to the analog signal. The PWM circuit receives M digital signals and M reference pulse signals, and outputs a PWM pulse according to the M digital signals and the M reference pulse signals. The light emitter receives the driving current and the PWM pulse during emission period of each of the N sub-frames.

Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.