Abstract: Integrated circuit devices, methods, and other embodiments associated with power throttling with temperature sensing and activity feedback are described. In one embodiment, an integrated circuit device includes temperature sensing logic, activity sensing logic, comparison logic, and signal logic. The temperature sensing logic is configured to output a temperature signal indicative of a temperature of a selected region of the device. The activity sensing logic is configured to output an activity signal indicative of a level of activity of a selected device function. The mode selection logic is configured to select the temperature signal or the activity signal. The comparison logic is configured to compare the selected signal to a series of threshold levels and output a comparison result. The signal logic is configured to generate a throttle signal based on the comparison result. The throttle signal is used to control a frequency of operation of a selected device component.

Abstract: A method for controlling a power consumption in a portable terminal and a portable terminal supporting the method are provided. The method includes receiving first data from at least one device, by a main processor; transmitting second data based on the received first data to a sub processor, by the main processor; receiving the second data from the main processor, and determining whether the main processor is in a sleep state, by the sub processor; and when it is determined that the main processor is in a sleep state, maintaining the sleep state of the main processor, receiving the first data from the at least one device, and controlling the at least one device based on the received first data and second data, by the sub processor.

Abstract: A power provisioning system includes power sourcing equipment having a plurality of ports. The power source equipment is configured to provide power to each of the plurality of the ports. A plurality of powered devices are each coupled to at least one of the plurality of ports. A controller is coupled to the power sourcing equipment through a network. The controller receives event information, determines that the event information corresponds to a first powered device of the plurality of powered devices and, in response, instructs the power sourcing equipment to provide power to the first powered device through the at least one of the plurality of ports that are coupled to the first powered device. In different embodiments, the event information may include an identification or authorization of a user, a determination that a scheduled area use is occurring, or the receiving of an emergency alert.

Abstract: Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device.

Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.

Abstract: A terminal apparatus and a controlling method thereof, the method comprising selecting, while the terminal apparatus is in an active mode, at least one channel from among a plurality of channels, receiving a broadcast signal corresponding to the selected channel, and outputting the received broadcast signal; storing, in a memory of the terminal apparatus, replay information related to the selected channel, and, in response to a power off command, converting the terminal apparatus from the active mode to a waiting mode; and in response to a power on command to convert the terminal apparatus from the waiting mode to the active mode, receiving a broadcast signal through the selected channel based on the replay information stored in the memory, wherein, in the waiting mode, power is supplied to the memory.

Abstract: A method of operating a system on chip (SoC) includes calculating a first residence time indicating an amount of time that at least one task resides in an execution queue in the SoC, wherein the at least one task is assigned to at least one core of a multi-core processor in the SoC, calculating a total unit residence time indicating an amount of time that all tasks other than the at least one task reside in the execution queue, calculating a second residence time for the at least one core by adding the first residence time of the at least one task and the total unit residence time, and adjusting at least one of an operating frequency and a voltage of the at least one core based on the second residence time.

Abstract: A trace array having features that provide reduced power consumption/power dissipation in processor circuits. The trace array circuit stores processor states during program execution and provides a resulting trace for subsequent analysis. The trace array includes power management features that, responsive to a control signal, reduce the power consumption of the trace array. A first state of the control signal indicates that the trace array circuit is storing states during the execution of the program and a second state of the control signal is set to enable the trace array for reading the collected states. The trace array may have dynamic read bit-lines and static write bit-lines to further reduce power consumption, and the pre-charge circuits that charge the dynamic read bit-lines may be selectively disabled in response to the first state of the control signal. Write-through may also be selectively disabled and optionally bypassed during state collection.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.

Abstract: A method, node and computer program for a client node (100) in a communications system for resetting of timer units, the client node comprising at least two timer units, the method comprising: for each of the timer units: detecting (S100) the timer unit (130) by a timer handling unit (110), registrating (S110) the detected timer unit (130) in a timer inventory (140) by the timer handling unit (110), the method further comprising: determining (S120) by the timer handling unit (110) which of the at least two timer units that expires first, determining (S130) a time T when the determined timer unit at the latest will be reset, and prior to the timer expiring, resetting (S140) at least one of the other timer units (130) with a new reset time based on the time T, thereby enabling longer radio and CPU sleep periods of the client node between reset of timer units.

Abstract: Presented herein are systems, methods, and computer-readable media for recording event times in particle detection scenarios. The systems, methods, and computer-readable media involve the identification of one facility device as a grandmaster clock among at least two facility devices of a facility device set, where the respective facility devices are selected from a facility device type set including a beam monitor; a neutron instrument; a neutron chopper; a nuclear reactor; a particle accelerator; a network router; and a user workstation. The system, method, and computer-readable medium also involve configuring the facility devices to synchronize a clock component with the grandmaster clock; and, upon detecting an event, retrieve from the clock component of the selected facility device an absolute event timestamp that is independent of event times of other events, and store a record of the facility event and the absolute event timestamp in the data store.

Abstract: Systems and methods for setting up carrier applications within a setup wizard are disclosed. In some implementations, a computing device launches an operating system setup wizard. The computing device launches, from the operating system setup wizard, a carrier-specific setup wizard. The computing device presents, from within the carrier-specific setup wizard, a setup interface for each of a plurality of carrier applications.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

Abstract: A new image being hosted by the device is modified. The modification is based on a main image operating the device. The device is booted from the modified image.

Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.