Abstract: A receiver circuit includes a deserialization unit, a sampling clock control unit and a sampling clock generation unit. The deserialization unit is configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals. The sampling clock control unit is configured to generate a delay control signal and a synchronization completion signal in response to the plurality of internal data signals and a first group of clock signals. The sampling clock generation unit delays the first group of clock signals and provides the delayed first group of clock signals as the sampling clock signals in response to the delay control signal, and provides a second group of clock signals having a phase leading by a predetermined amount with respect to the first group of clock signals, as the sampling clock signals in response to the synchronization completion signal.

Abstract: An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Abstract: Power regulator circuitry that can provide a regulated power signal. The power regulator circuitry may include data processing circuitry configured to determine the regulated power signal to arbitrate power supply requirements of first and second powered devices according to power supply information associated with the first and second powered devices. The power regulator circuitry may also include output circuitry configured to output the regulated power signal to one or both of the first and second powered devices.

Abstract: According to one embodiment, an information processor is equipped with an information processor terminal that contains a main control unit that processes information, an IO control unit that supplies electrical power to connected equipment (peripheral devices) and that controls communications, and a power supply unit that supplies electrical power, as well as a first switching circuit that connects a plurality of batteries and supplies electrical power to the main control unit, a second switching circuit that connects a plurality of batteries and supplies electrical power to the IO control unit, and a battery unit that contains a battery control part that controls the first switching circuit and the second switching circuit.

Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.

Abstract: An information processing apparatus includes a processor that executes an instruction stored in a fixed address area in a storage part; the storage part that stores a first startup program and a second startup program, contents of the second startup program being different at least partially from those of the first startup program; and an address conversion part that, when the processor carries out a predetermined startup different from an ordinary startup that is carried out at a time of starting power supply to the information processing apparatus, converts an address included in a read instruction issued by the processor indicating a storage area that stores the first startup program into an address indicating an other storage area that stores the second startup program, and sends the converted address to the storage part.

Abstract: A method, system, and information handling system provides better system power consumption of a redundant power system having a plurality of power supply units (PSUs) by taking into consideration each PSU's sleep power consumption during selection of one or more PSUs to place into a “hot spare” sleep mode. For each PSU, power efficiency data at different load ratings are measured and stored. During the PSU selection, a calculation of system power consumption is conducted on each of several configurations where a different PSU is hypothetically disabled. Each calculation takes into consideration both the sleep power consumption of a disabled PSU and power efficiency data of an enabled PSU. Selection of one or more PSUs to disable is determined according to the configuration yielding the lower or lowest system input power consumption based on the results of the calculations.

Abstract: Arrangements for executing enterprise resource planning software in a plurality of modes are presented. A graphical user interface may allow an administrator to select from the plurality of modes for executing the enterprise resource planning software, such as a test mode and a production mode. A selection of one of the modes may be received. The selected mode may be linked with a particular initialization file that is used to initialize the enterprise resource software. The enterprise resource planning software may be initialized and run using the selected initialization file.

Abstract: A microcomputer of an ECU which is a master determines whether to turn on or off the power supply of a slave ECU, and outputs a power supply control signal indicating power-on/off via serial communication on the basis of the result of determination. A signal superposition circuit accepts the output power supply control signal and transmits the accepted power supply control signal to a CAN bus to which a CAN transceiver is connected. In the slave ECU, a signal separation circuit individually receives a CAN communication signal and a serial communication signal transmitted to the CAN bus, while an input/output control circuit to which the serial communication signal is input as the power supply control signal outputs a signal to the power supply circuit to control power-on/off of the microcomputer.

Abstract: A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.

Abstract: A method and apparatus for power-efficiency management in a virtualized cluster system. The virtualized cluster system includes a front-end physical host and at least one back-end physical host, and each of the at least one back-end physical host comprises at least one virtual machine and a virtual machine manager. Flow characteristics of the virtualized cluster system are detected at a regular time cycle, a power-efficiency management policy is generated for each of at least one back-end physical host based on the detected flow characteristics, and the power-efficiency management policies are performed.

Abstract: A maximum and a minimum performance operating limit is set for a plurality of processing units in accordance with a set of one or more rules enforced by the performance supervisor. Each of the plurality of processing units has logic configured to ensure a request for an operational setting complies with the maximum and minimum operating limits. Each of the plurality of processing units is configured to output a request for a limit compliant operational setting to a performance controller. The performance controller is configured to actuate the operational request.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: An information processing apparatus capable updating firmware thereof, while reducing power consumption. In a case where an image forming apparatus as an information processing apparatus is in a power switch off mode in which a power switch operable by a user is kept turned off and where a setting to permit execution of firmware update has been set by the user, the image forming apparatus stops power supply for execution of processing other than processing performed by a network I/F. When a firmware update request is received by the network I/F, the image forming apparatus restores power supply for execution of firmware update.

Abstract: An uninterruptible power system and a power control system thereof are disclosed. The power control system includes the uninterruptible power system and a computer system. The uninterruptible power system supplies power to the computer system and includes an external power adaptor, a battery module, a first switch module, a second switch module, and a switching control module. When external power is input, the external power is transmitted to the computer system via the external power adaptor. When the external power is not input, the first switch module switches automatically to supply a backup power signal from the battery module to the computer system. When the external power is not input and a control signal is not received from the computer system, the switching control module controls the second switch module to electrically disconnect a connection between the computer system and the battery module.

Abstract: A computer device and a boot method thereof are provided. The method is applicable to a computer with a Basic Input Output System (BIOS) and an Operating System (OS). The computer includes a chassis and a memory. In the boot method, after the computer is started, it is judged whether the chassis is opened in an interval from the last boot time to the current boot time. If the chassis is not opened in the interval from the last boot time to the current boot time, the BIOS does not detect hardware elements connected to the computer to obtain setting and parameter values of each hardware element, but reads directly the setting and parameter values of each hardware element that are stored in the memory last time, initializes each hardware element, transmits the setting and parameter values to the OS, and executes the OS to complete the boot process.

Abstract: There is provided a power control apparatus including a power supply control unit that executes power supply control with respect to a device connected to a power supply line, a connector that is connected to a cable to perform versatile communication between the power supply control unit and an external device, and a switch that is provided at a predetermined position of a circumferential portion of the connector and physically intercepts the versatile communication between the power supply control unit and the external device.

Abstract: Systems and methods for reducing problems and disadvantages associated with multiple boot methods are disclosed. In accordance with an embodiment of the present disclosure, an information handling system comprises a processor and a memory communicatively coupled to the processor. The information handling system also comprises an access controller communicatively coupled to the processor. The access controller is configured to retrieve non-bootable executable instructions and combine the non-bootable executable instructions with a boot loader associated with a boot method to generate a bootable image associated with the boot method. The access controller is further configured to present the bootable image to the information handling system such that the bootable image is configured to be booted by the information handling system using the boot method.

Abstract: Disclosed and claimed is a method of improving the effective frequency stability of a frequency reference, wherein an algorithm utilizing temperature frequency hysteresis characterization values or hysteresis model parameters, and temperature history data, is used to account for effects of temperature frequency hysteresis. Devices and manufacturing systems are also claimed.

Abstract: Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.