Abstract: A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses.

Abstract: A method and an apparatus for controlling an operation voltage of a processor core and a processor system including the same are provided. The apparatus for controlling an operation voltage of a processor core includes a voltage supplier and an operation voltage searching core. The voltage supplier supplies the operation voltage to the processor core. The operation voltage searching core requests the processor core to execute a program, and controls the operation voltage based on whether the program has been normally operated.

Abstract: A communication system operating with a battery is provided. Each node of the system is operable in a sleep mode and a normal mode, outputs a transition availability notice frame indicating whether or not the node is permitted or prohibited to transition to the sleep mode. At least one node is a monitor node. Upon receipt of a transition availability notice frame indicating prohibition of transition to the sleep mode while the battery is in a low voltage state, the monitor node stores sender information in a non-volatile memory, the sender information identifying what node is a sender node sending this transition availability notice frame.

Abstract: A BIOS updating method determines whether to allow a current BIOS version to be upgraded or downgraded to a target BIOS version according to a dependency description recorded in a BIOS updating program or a dependency description recorded in an SMBIOS. If all of the BIOS versions recorded in the dependency description are not between the current BIOS version and the target BIOS version, the BIOS updating program allows the current BIOS version to be upgraded or downgraded to the target BIOS version. If at least one of the BIOS versions recorded in the dependency description is between the current BIOS version and the target BIOS version, the BIOS updating program forbids the current BIOS version to be directly upgraded or downgraded to the target BIOS version.

Abstract: A method and apparatus for power-efficiency management in a virtualized cluster system. The virtualized cluster system includes a front-end physical host and at least one back-end physical host, and each of the at least one back-end physical host comprises at least one virtual machine and a virtual machine manager. Flow characteristics of the virtualized cluster system are detected at a regular time cycle, a power-efficiency management policy is generated for each of at least one back-end physical host based on the detected flow characteristics, and the power-efficiency management policies are performed.

Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.

Abstract: An information processing system that includes a casing and a plurality of other casings, the casing containing a plurality of information processing devices which are respectively connected through communication paths to a plurality of other information processing devices contained in the plurality of other casings, wherein the plurality of information processing devices each includes; a detection unit that detects connection states of all target communication paths to and from a plurality of target information processing devices contained in target casings, among the plurality of other casings, in a range of influence, such as commonly cooled by a same cooling device; a holding unit that holds the connection state information of all the target communication paths detected by the detection unit; and a control unit that controls power supplies for the information processing device, based on the connection state information the holding unit holds.

Abstract: An electronic device includes a processor coupled with at least two loaded media. The electronic device can work at a first working mode and a second working mode. When the electronic device works at the first working module, the processor selects one loaded media and controls the selected loaded media to execute a function according to a first manual operation received by an inputting unit of the electronic device. When the electronic device works at the second working module, the processor controls each of the at least two loaded media to execute a common function according to a second manual operation received by the inputting unit.

Abstract: In response to a warning that power may be interrupted, a non-volatile data storage sub-system of a host computer system re-orders machine readable instructions that the non-volatile data storage sub-system is going to perform. This re-ordering of instructions decreases the probability that important data will be lost. The re-ordering of instructions is performed according to rules.

Abstract: A temperature control method of a semiconductor device is provided. The temperature control method includes detecting a temperature of the semiconductor device; activating a reverse body biasing operation in which a body bias voltage applied to a function block of the semiconductor device is regulated, when the detected temperature is greater than a first temperature level; and activating a thermal throttling operation in which at least one of a frequency of a driving clock provided to a function block of the semiconductor device and a driving voltage applied to the function block of the semiconductor device is regulated, when the detected temperature is greater than a second temperature level that is different than the first temperature level.

Abstract: An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

Abstract: A server system and controlling method for an operation timing after being powered up are disclosed. The sever system controls a reset signal to have a voltage lower than a first voltage value by introducing a voltage monitoring module when a work power lower than a voltage threshold. On the other hand, when the work power voltage increases to higher than the voltage threshold of the voltage monitoring module, the voltage monitoring module controls the reset signal voltage to be higher than a second voltage value, whereby achieving in a technical efficacy of stable initialization and reset of the server.

Abstract: Methods, systems, and computer-readable media are provided for offloading services and functionalities from a main host central processing unit (CPU) of a computing device to a dedicated power-efficient offload engine, thereby enabling a longer battery life for the device and an enhanced set of features.

Abstract: Various embodiments of methods and systems for idle state optimization in a portable computing device (“PCD”) are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.

Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract: Systems and methods for automatic failover in modular chassis systems. In some embodiments, a modular chassis includes a chassis management controller and a plurality of server blades. A first of the plurality of server blades may be configured to detect an internal fault to and to transmit a corresponding alert message to the chassis management controller via a midplane connection. Moreover, the chassis management controller may be configured to initiate a migration procedure to transfer one or more workloads from the first server blade to a second of the plurality of server blades.

Abstract: A computer program product includes computer usable program code for: identifying a plurality of power distribution units (PDUs) disposed in a rack, wherein each PDU receives power from a main power source and includes a circuit breaker; identifying a plurality of devices disposed in the rack, wherein each device receives power from one of the PDUs, and wherein the plurality of devices are selected from server nodes, network switches and external data storage devices; obtaining vital product data from a service processor in each device, wherein the vital product data identifies the device by a model identification code; and powering on, for each of the PDUs, the plurality of devices that are connected to the PDU in a sequence to prevent an inrush current from tripping the circuit breaker within the PDU, wherein the sequence powers on devices in order of ascending commonality of the model identification code.

Abstract: Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.