Abstract: A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device.

Abstract: A portable electronic apparatus and a power management method are disclosed. The portable electronic apparatus comprises a processor and an embedded controller (EC). The EC determines whether the processor starts a throttling mechanism according to a current power consumption, a proportional term, a last power consumption, a lower bound, a delta power and a derivative term. The EC determines whether the processor cancels the throttling mechanism according to the current power consumption, the lower bound, a count that the power consumption is lower than the lower bound, and an integral term.

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract: A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.

Abstract: A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract: A computer system and an operating method thereof are disclosed herein. The operating method includes determining an operating state of a logic device; receiving a present power level of a mainboard; comparing the present power level of the mainboard with a present power level threshold of the mainboard, and determining whether to generate an alert signal accordingly; selectively providing the alert signal to a system controller or a baseboard management controller (BMC) according to the operating state; and adjusting, through one of the system controller and the BMC, whichever receives the alert signal, the present power level threshold of the mainboard.

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.

Abstract: Electronic device comprising: processing unit including accepting part accepting processing request from external device and executing process specified by request; secondary battery connected with external power source; and power-source device transitioning to operating state when request is accepted in waiting state, and transitioning to waiting state when processing unit completes executing process, wherein, in waiting state, power supply from external power source to processing unit is stopped and secondary battery supplies power to accepting part, and in operating state, power is supplied from external power source to processing unit.

Abstract: Even after power-down, distinction between a transition from a PLL normal-oscillation state and a transition from a PLL self-oscillation is allowed. A semiconductor device includes a first region which, after having transited from a power-supply state to a power-down state, returns to the power-supply state again, a second region which holds a power source voltage regardless of power-down of the first region, and an oscillator which generates a first clock signal supplied to the first region. The first region includes a PLL circuit. The second region includes an information holding unit capable of holding information which can distinguish whether the operation mode of the PLL circuit is a PLL normal-oscillation mode or a PLL self-oscillation mode, and determines the operation mode of the PLL circuit when the first region has returned from the power-down state to the power-supply state, according to the information held in the information holding unit.

Abstract: A rack-power control module (RPC) module is used for allowing a local storage partition, located on a local server, for controlling a destination storage partition, located on a destination server, by piggybacking commands on power alerts issued by the RPC module in a clustered storage system.

Abstract: Methods and systems for powering-off a wireless communication device from a linked device are provided. A device can transmit a wireless communication signal to a linked device to instruct the linked device to power-off. In this manner, the user need only turn off one device manually which results in all linked devices being powered off. This process can be initiated by a user through a device directly linked with the device to be powered-off or through a device that is indirectly connected, through one or more wireless communication networks, with the device to be powered-off. This process can also be automatically initiated by a device when a set of predetermined conditions exist. Once instructed to do so, a device can initiate a predetermined power-off process which can involve terminating any ongoing functions and turning off various subsystems. In accordance with the present invention, a user can initiate a power-off of all the devices on a wireless communication network through a single device.

Abstract: The present disclosure provides a method for configuring a basic application function of an intelligent terminal.

Abstract: A power throttling queue includes a queue and a throttling circuit. The queue has multiple entries. Each entry has a data field and a valid field. The multiple entries include a first portion and a selectively disabled second portion. The throttling circuit is coupled to the queue, and selectively disables the second portion in response to a number of valid entries of the first portion.

Abstract: An apparatus and method is described herein for reducing noise in a power distribution network for an interface. The power distribution network is characterized. And based on that characterization, worst case patterns for the interface are predicted and avoided. As one example, characterization includes providing a stimulus, such as a step function stimulus, and determining a mathematical function response, such as a step function response. Then, based on the step function response, a resonant frequency for the power distribution network is determined; from which patterns that cause the resonant frequency are identified/predicted. And when identified patterns are detected, they are scrambled or manipulated to avoid causing a worst-case noise scenario in an interface's power distribution network.

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node.

Abstract: A communication device includes a main control part configured to receive and process an image signal; a first network control part configured to convert data input from an external device into the image signal and provide the main control part with the image signal; a sub control part configured to detect a power-on command; and a second network control part configured to control communications with the external device via a network to provide the first network control part with data input from the external device. Power supplies to the main control part, the sub control part, the first network control part and the second network control part are independently controlled.