Abstract: Some embodiments of the invention provide novel methods for removing acute angles form routes in a design layout. The method reacts a route with several segments. It then identifies an acute angle between first and second contiguous segments of the route. The method next inserts a third segment between the first and second segments, where the third segment has an associated shape that fills the acute angle between the first and second segments.

Abstract: A method is provided for correcting rule violating areas of a photomask using a digital representation of the photomask. The method includes identifying violating areas of the photomask from a digital representation of the photomask. The violating areas include areas that violate a minimum width rule and/or areas that violate a minimum space rule for the photomask. The violating areas are then manipulated for the purpose of eliminating the violating areas. They are manipulated differently based on whether the violating area lies inside a design shape of a layout pattern to be imaged using the photomask and/or whether the violating area lies outside the design shape.

Abstract: An algorithm C description describing an algorithm of computation or control of a logic circuit in a C language is split into a plurality of states in units of processing, and the execution order of the split processing is described as state transition, to generate a functional C description with a control description embedded therein. A clock description as the conception of time is inserted in the functional C description, to be converted into a RT level C description. The RT level C description is converted into a RT level description in HDL with an existing conversion tool.

Abstract: In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: An invariant checking method and apparatus using binary decision diagrams (BDDs) in combination with constraint solvers for determining whether a system property is an invariant of a system description. The invariant checking method receives system descriptions and system properties and transforms them into a model formula. Specific variables are eliminated from the model formula and a corresponding output formula is generated. The output formula is transformed into a logic formula by substituting a new logic variable for each integer constraint in the output formula. A constrained BDD is constructed from the logic formula. The constrained BDD uses a heuristic algorithm to order the logic variables in the paths leading to true or false. A constraint solver is applied to the integer constraints that correspond to the occurrences of logic variables in the BDD paths, which determines whether the system property is or is not an invariant of the system description.

Abstract: A drive mechanism for an injection device is disclosed in which piston means 306 are selectively driven to expel medicament from within a medicament cartridge 40. A drive mechanism for controlling the movement of the piston means is described comprising a housing 302, a shuttle 300 located for movement within the housing 302 along a longitudinal axis between a first position and a second position, and drive means to move the shuttle 300 within the housing 302. A gear component 304 is located within the housing 302 for rotation about the longitudinal axis and associated with the piston means 306, movement of the shuttle 300 between each of the first and the second positions causing movement of the piston means 306.

Abstract: A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.

Abstract: Some embodiments provide a method of computing the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a polygon that encloses the set of states. It then identifies vectors to project from the vertices of the polygon based on a model that allows penalizes measurements in certain directions more than other directions. Based on the projected vectors, the method then identifies the estimated distance.

Abstract: A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices (“sinks”) within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition.

Abstract: A method for designing semiconductor integrated circuits that efficiently optimizes clock skews in a plurality of clock modes in the case of designing semiconductor integrated circuits having a plurality of clock modes. A plurality of clock paths in each of a plurality of clock modes are detected from layout data for a semiconductor integrated circuit. Delay time in all elements on each of the plurality of clock paths detected is collected. A delay adjustment position is set on each of the plurality of clock paths detected. An optimum delay value at the delay adjustment position on each of the plurality of clock paths is calculated by considering delay time at the set delay adjustment position as a nonnegative variable, by formulating a linear expression for each of the plurality of clock paths by use of this variable and the collected delay time in all of the elements, and by working out the linear expression.

Abstract: A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon. Thus, the static timing analysis can be accomplished efficiently.

Abstract: Light intensity values only of the vicinity of a specified portion, that is, for example, based on a prescribed value, an area where the distance between edges of an object to be corrected is equal to or shorter than the prescribed value are calculated, and the object to be corrected is corrected based on the light intensity values.

Abstract: A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.

Abstract: A system is provided for determining voltage at the output of a gate in an integrated circuit. The system locates a gate within the integrated circuit and looks up a set of output current waveforms as a function of time for different effective capacitances at the gate's output. The system applies each output current waveform to its corresponding effective capacitance to calculate a first set of output voltages and applies each output current waveform to a model of the net coupled to the output of the gate to calculate a second set of output voltages. For each time step in a series of time steps, the system selects an output current waveform for which a voltage in the first set of output voltage waveforms matches a voltage in the second set of output voltage waveforms. The system uses the selected output current waveform to determine the output voltage.

Abstract: A simulation result verification method of the present invention compares a simulation result representing the relationship between the time and the output state at a given node, with condition information specifying the conditions for the output state of the given node over time, and evaluates the same. Accordingly, it is possible to determine whether the simulation result and the condition information agree with each other and it is not necessary to visually verify the relationship between the simulation result and the threshold value, thereby shortening the verification time and reducing possible errors in visual verification to a low level.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Abstract: A method of extracting circuit parameters from picosecond-scale photon timing measurements is disclosed. In one embodiment, the method is implemented by a system that comprises a photomultiplier, a data acquirer, and a processing module. The photomultiplier detects photons emitted from current-carrying channels in an integrated circuit, and associates a detection position and a detection time with each detected photon. The data acquirer receives position and time signals from the photomultiplier, and further receives a trigger signal. The data acquirer determines a relative detection time for each photon by combining the time and trigger signals. The data acquirer gradually compiles the photon detection data and makes it available to the processing module. The processing module responsively determines optimal values for a parameterized model of the data. The model is preferably based on non-homogeneous Poisson process statistics, and may employ a maximum likelihood approach to estimating the optimal values.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: Apparatus, method and program product for evaluating design code of an integrated circuit. A program assigns an identifier to a cell based upon a cell characteristic. The program catalogs the identifier in a database configured to store and recall the identifier and characteristic along with additional properties that pertain to the cell. The program may associate the identifier or characteristic with a cell embedded in the design code.