Abstract: A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important properties of generated designs. The use of the visualization and data mining technique significantly reduces the time needed for analysis of design space and decision on which design point to choose for implementing into a circuit design.

Abstract: In a system of manufacturing a semiconductor integrated circuit, a client, a data-managing center, a designing center, and a manufacturing center are connected together via the Internet. The data-managing center has a cost/number-of-days database, a reservation status database, and a design/manufacture status database. Each of the centers uses information contained in the databases of the data-managing center, performs two-way communication with the client, and thereby progresses the production of the semiconductor integrated circuit.

Abstract: A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements or performs a set of two or more functions. Some embodiments provide a method for producing a circuit description of a design that (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the replacement sub-network in certain conditions. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Abstract: A ladder circuit editing system inputs and edits a sequence program for a program controller in the form of a ladder diagram. The ladder circuit editing system has an unavailable area storing at least one inputted circuit pattern and an available area storing a new circuit pattern, and successively inputs circuit patterns from the available area. The ladder circuit editing system includes a circuit pattern extracting means, a display means, and a copying means. The circuit pattern extracting means compares a circuit element from a circuit pattern stored in the available area with a circuit element from a circuit pattern already stored in the unavailable area, and extracts a circuit pattern containing a circuit element that agrees with a stored one. The display means displays the extracted circuit pattern on an input screen. The copying means copies the extracted circuit pattern into the available area according to an operator's entry.

Abstract: A design analysis tool performs path extraction translation and false path identification functions. The design analysis tool is utilized with a conventional automated test pattern generator and timing analysis tools. By checking for four specific criteria, a fast and efficient way to detect whether a circuit path is false or active is accomplished. A final value condition is checked and, if that test is met, a side value propagation condition is checked. Assuming both tests result in the path still being active, the test is terminated. If the side value propagation conditions are not satisfied, then an initial value condition and a slower path condition is checked. The checks are made to determine whether or not conditions exist in the path that makes the path false. The information may be obtained quickly from the timing analysis information and the result of the ATPG tool.

Abstract: A method may be used to insert or to engage solid objects into human bodies, and includes a syringe having a bore and a front opening to receive the solid objects. The syringe may then be engaged into the human bodies, and may then be disengaged from the human bodies, to allow the solid objects to be retained within the human bodies after the syringe is disengaged from the human bodies. It is preferable that an extension is extended from the solid objects, and/or bent relative to the solid objects, to retain the solid objects within the human bodies. The solid objects may include a material, such as a fluid or powder medicine received within a capsule.

Abstract: A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective function. The grouping produce a plurality of cell clusters. The model formed may be a binary tree. The curvature of the objective function for each of the cell clusters is estimated. Interactions between said cell clusters are described as a relation. A set of preconditioning values which achieves a separation of variables of the relation is determined. The preconditioning may be applied to a conjugate gradient placement process to advantageously decrease the number of iterations required to produce an optimized placement of the cells.

Abstract: A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

Abstract: Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The space has several dimensional states. The method identifies several pairs of wedge vectors. Each vector has a tail, and each wedge-vector pair includes two vectors that are connected at their tails. The method assigns locations in the first state for the tails of at least some of the identified wedge-vector pairs. The method then uses the wedge-vector pairs that have assigned tail locations to propagate the first cost function.

Abstract: A method and system of constrained optimization with linear constraints to remove overlap among cells of an integrated circuit. A coarse placement using well known methods may provide an initial placement of cells. Overlapping cells are separated. Any cell moved to its initial placement may be fixed so as not to be moved during subsequent placements. A plurality of linear inequalities representing allowable placements of a plurality of cells of a layout is generated. An objective function measuring cell movement subject to the constraints of the plurality of inequalities is minimized. The objective function minimizes cell movement from the initial cell placement. In this novel manner, large and small cells may be automatically simultaneously placed, deriving speed and quality advantages over prior art methods.

Abstract: An injection device for injection of a medicament from a first medicament cartridge (40) is disclosed. The injection device comprises a drive mechanism (42) for selectively dispensing the medicament from the first medicament cartridge (40), a dial dose mechanism (12, 14) by which a user may determine a required dose of medicament to be dispensed, an electronic control unit for controlling the operation of the drive mechanism (42) in response to the dial dose mechanism (12, 14) and a display panel (10).

Abstract: A design verifier includes a bounded model checker, a proof partitioner and a fixed-point detector. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If a counterexample is found, the bounded model checker selectively increases K and verifies the property to the new larger depth using the original constraints. If no counterexample is found, the proof partitioner provides an over-approximation of the states reachable in one or more steps using a proof generated by the bounded model checker. The fixed-point detector detects whether the over-approximation is at a fixed point. If the over-approximation is at a fixed-point, the design is verified. If the over-approximation is not at a fixed point, the bounded model checker can iteratively use over-approximations as a constraint and verify the property to a depth K.

Abstract: Structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD. The re-programmable logic block is tested without using the one-time programmable resources needed for implementing user circuits, by including a multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion of the PLD. In some embodiments, a tester operating at a first and lower clock frequency can be used to test a re-programmable logic block operating at a second and higher clock frequency. In some of these embodiments, the one-time programmable fabric is tested at the first clock frequency.

Abstract: A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

Abstract: A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.

Abstract: Customer data relating to the location and character of features (e.g., conductive pads to which electronic parts are soldered on a printed circuit board) are stored in a digital form (e.g., as “Gerber data”). A library of footprints that characterize the features is created from this data. A footprint filter and a modification parameter are then applied to the footprint library to select footprints for modification and to make a desired change to the selected footprints. In a printed circuit board embodiment, apertures in a stencil designed for printing solder on the printed circuit board are then cut in accordance with the footprints. Data representing all the apertures to be cut in the stencil can be moved or scaled to compensate for variations in the printed circuit board manufacturing and stencil manufacturing processes. The above-described method can be carried out via instructions stored as software code on a computer-readable medium.

Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

Abstract: A venous catheter comprises a flexible plastic tubular body having a center lumen. A plurality of drainage openings are formed in a reinforced opening-containing section of the body. Reinforcement is embedded in the body within the reinforced opening-containing section. The reinforcement includes a series of annular ringlets each formed of a few tightly wound helical turns. The ringlets can be non-interconnected, or interconnected by a helical connecting part by forming the ringlets and connecting parts from a continuous wire. The drainage openings are disposed in spaces formed between successive ringlets.

Abstract: A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.

Abstract: A method and apparatus for simulating multiple stimuli using symbolic encoding. In one embodiment, the method comprises encoding a plurality of sets of stimulus to create a symbolic stimulus, symbolically simulating a device under test, including applying the symbolic stimulus to the device under test, and outputting a symbolic result from the device under test in response to the symbolic stimulus.