Patents Examined by A. M. Thompson
  • Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks
    Patent number: 7089518
    Abstract: Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at the boundary between the two independently clocked subsystems with a behavior model, said behavioral model comprising data receiver time delays.
    Type: Grant
    Filed: May 8, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dean Gilbert Bair, Edward James Kaminski, Jr., Bradley Sterling Nelson
  • Method and system for performing placement on non Manhattan semiconductor integrated circuits
    Patent number: 7089519
    Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: August 8, 2006
    Assignee: Cadence Design System, Inc.
    Inventor: Steven Teig
  • Methods and apparatus for defining power grid structures having diagonal stripes
    Patent number: 7086024
    Abstract: A method for defining and producing a power grid structure of an IC having diagonal power and ground stripes. Stripes are placed in a 45° or 135° diagonal direction in relation to an IC layout's x-coordinate axis so that the stripes will be placed in a 45° or 135° diagonal direction, respectively, in relation to the bottom boundary of the resulting IC. The diagonal power and ground stripes are beneficial to diagonal signal wiring. The stripes may be placed across one layer of the IC or across more than one layer of the IC. The diagonal power stripes may have varying widths and/or varying spacing widths on a layer of the IC. The diagonal ground stripes may have varying widths and/or varying spacing widths on a layer of the IC.
    Type: Grant
    Filed: June 1, 2003
    Date of Patent: August 1, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hengfu Hsu, Steven Teig, Akira Fujimura
  • Method for reducing a parasitic graph in moment computation in VLSI systems
    Patent number: 7082583
    Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Weiqing Guo, Sandeep Bhutani
  • Automated analysis of RTL code containing ASIC vendor rules
    Patent number: 7082584
    Abstract: A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Juergen Lahner, Kiran Atmakuri, Kavitha Chaturvedula, Balamurugan Balasubramanian, Krishna Devineni, Srinivas Adusumalli, Randall P. Fry, Gregory A. Pierce
  • Method of estimating path delays in an IC
    Patent number: 7082587
    Abstract: To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: July 25, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pinhong Chen, Chin-Chi Teng
  • Creating polynomial division logical devices
    Patent number: 7080348
    Abstract: A method of creating a logical device performing polynomial division includes using a hardware description language to build code directly describing synthesizable logic for performing the polynomial division. The logic is then implemented on a target device. The code receives as inputs a parameter identifying a polynomial and a parameter identifying a number of data bits for which the polynomial division is performed. For a given n-degree polynomial, performing the polynomial division includes calculating a next n-term remainder for a data unit having d terms.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: July 18, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Paul Savage
  • Automatic clock gating insertion in an IC design
    Patent number: 7080334
    Abstract: A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the signature includes an indication of feedback element instance type for each feedback element instance in the feedback loop, feedback position at each instance of a feedback element type in the feedback loop and a control signal for each instance of a feedback element type in the feedback loop; evaluating the feedback loop signature so as to generate associated stimulus logic; generating associated load logic; and inserting the generated stimulus logic to control a clock input to the sequential element; and inserting the generated load logic to provide a data input to the sequential element.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: July 18, 2006
    Assignee: Incentia Design Systems Corp.
    Inventors: Yong Fan, Steve C. Huang, Ihao Chen
  • Apparatus and method for selecting a printed circuit board
    Patent number: 7080343
    Abstract: An apparatus and method for selecting an optimum printed circuit board in terms of its intended use before placement of components on the printed circuit board, information about components to be mounted on the printed circuit board, and an outer size of the printed circuit board is provided. The apparatus includes an input section for inputting information, a storing section for storing information, an arithmetic section for performing an arithmetic calculation using the information stored in the storing section, a display section, and a control section. By deriving an index in the arithmetic section, selection of the optimum printed circuit board can be accomplished.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Junko Asai, Toshio Mukai, Toshihiko Nishio
  • Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization
    Patent number: 7076756
    Abstract: In a layout design method for a semiconductor integrated circuit, a cell layout library is provided which stores structure information of functional cells and a plurality of groups of filler cells, each filler cell acting to fill space between the functional cells. The functional cells are arranged on a layout based on the structural information from the layout library. The filler cells of any of the plurality of groups are arranged selectively based on the structural information from the layout library so that the filler cells are arranged in channel regions where the functional cells are not located on the layout, each channel region being located at a predetermined distance from signal lines on the layout.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: July 11, 2006
    Assignee: Ricoh Company, Ltd.
    Inventor: Junji Ichimiya
  • Identification and implementation of clock gating in the design of integrated circuits
    Patent number: 7076748
    Abstract: Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 11, 2006
    Assignee: Atrenta Inc.
    Inventors: Bhanu Kapoor, Sanjay Churiwala, Joy Banerjee
  • Solving constraint satisfiability problem for circuit designs
    Patent number: 7073143
    Abstract: A method for generating a test vector for functional verification of circuits includes providing a representation of a circuit, where the representation includes a control logic component and a datapath logic component. The method also includes reading one or more vector generation targets, and performing word-level ATPG justification on the control logic component to obtain a control logic solution. The method further includes extracting one or more arithmetic functions for the datapath logic component based on the control logic solution, and solving the one or more arithmetic functions using a modular constraint solver. The modular constraint solver is based on a modular number system.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: July 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventor: Chung-Yang Huang
  • Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space
    Patent number: 7073151
    Abstract: Some embodiments of the invention provide a method for identifying a path in a design layout. Based on the design layout, the method defines a triangulated graph that has sets of source and target states and two orthogonal axes. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths in the graph until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path is an expansion to a line that is not aligned with the axes of the graph.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: July 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Gate estimation process and method
    Patent number: 7073156
    Abstract: A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Urine absorbent pouch for male incontinence
    Patent number: 7066920
    Abstract: A urine absorbent pouch for male incontinence which completely surrounds the patient's penis, thereby minimizing the patient's exposure to wetness, is provided. The pouch is constructed from a piece of material which has a hole portion and a continuous portion, the hole portion containing a hole which is adapted to receive a patient's penis. A plurality of sealing means are located along the edges of the hole portion so when the sealing means are sealed onto the continuous portion, there is minimal contact between the sealing means and the patient. Additionally, a urine absorbent pouch for male incontinence can be created from a commercially available baby diaper by cutting a hole in the diaper and attaching additional sealing means to the portion of the diaper with the hole.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: June 27, 2006
    Inventor: Anthony Mula
  • Method and apparatus for identifying a path between source and target states in a space with more than two dimensions
    Patent number: 7069531
    Abstract: Some embodiments of the invention provide a method for identifying a path between a set of source states and a set of target states in a space with more than two dimensions. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. At least some of the states are non-zero dimensional states. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths to other states in the space until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path includes an expansion in more than two dimensions of the space.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 27, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Approach for routing an integrated circuit
    Patent number: 7065729
    Abstract: A computer-implemented approach for routing an integrated circuit using non-orthogonal routing is accomplished during two phases: a global routing phase and a detailed routing phase. During global routing, routing indicators, in the form of hint polygons, are added to the integrated circuit layout and strategy lists, that include bias directions and straying limits, are generated for the new wires to be added. The hint polygons and strategy lists are used during detailed routing to aid in placing the new wires. If obstacle conflicts or insufficient space problems prevent the detailed routing of a new wire, then an obstacle resolution portion of global routing is used to resolve the obstacle conflict and/or provide additional space in the integrated circuit layout to route the new wires.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: June 20, 2006
    Inventor: David C. Chapman
  • Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane
    Patent number: 7065732
    Abstract: A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Victor Konrad, Vivek Joshi
  • System and method for guiding and optimizing formal verification for a circuit design
    Patent number: 7065726
    Abstract: The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: June 20, 2006
    Assignee: Jasper Design Automation, Inc.
    Inventors: Vigyan Singhal, Joseph E. Higgins, Chung-Wah Norris Ip, Howard Wong-Toi
  • Pattern correction method of semiconductor device
    Patent number: 7065739
    Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachiko Kobayashi, Toshiya Kotani, Satoshi Tanaka, Susumu Watanabe, Mitsuhiro Yano