Abstract: A drive mechanism for an injection device is disclosed in which piston means are selectively driven to expel medicament from within a medicament cartridge. The drive mechanism comprises a drive means (270), first means (278) associated with the drive means, second gear means (274) being moveable between a first position in wich only movement along its longitudinal axis is permitted and a second position in which the second gear means (274) is free to rotate about the longitudinal axis, the piston means (280) being associated with the second gear means (274), a housing (276) within which the first gear means (278) and the second gear means (274) are constrained for movement, and biassing means (282) located between the housing (276) and a second gear means (274) to bias the second gear means (274) to the first position.

Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Abstract: In the exposure method which carries out optical proximity correction processing for exposure data having a plurality of exposure patterns and exposes a sample in accordance with such corrected exposure data, the exposure patterns to be corrected are converted, in the optical proximity correction processing, into a minus objective pattern and a minus pattern to be deleted from the minus objective pattern, to form corrected exposure data. And, the minus pattern is deleted from the minus objective pattern of the corrected exposure data to bitmap a corrected exposure pattern, to expose a sample in accordance with such bitmapped corrected exposure pattern.

Abstract: A semiconductor circuit designing apparatus includes a circuit design unit executing and an inspection item database section. The circuit design unit executes a logical design of a semiconductor integrated circuit. In the inspection item database section a circuit feature of the semiconductor integrated circuit corresponds to an inspection item of an inspection to be executed before a layout design of the semiconductor integrated circuit is executed. The circuit design unit generates target circuit feature information indicating the circuit feature of a target semiconductor integrated circuit of the semiconductor integrated circuit of which the logical design should be executed. The circuit design unit obtains a target inspection item of the inspection item corresponding to the target circuit feature information from the inspection item database section. The circuit design unit executes the logical design of the target semiconductor integrated circuit in reference to the target inspection item.

Abstract: A method and system are disclosed for efficiently and effectively toggling logic states of chip elements during a burn-in process of a digital integrated circuit chip. A set of IDDQ patterns are generated by a design simulation tool, based on the design of the chip, during a simulation of the design. The set of IDDQ patterns are translated to a set of burn-in patterns that are compatible with a pattern format of a burn-in board using a pattern translation tool. The set of burn-in patterns are stored in memory on the burn-in board and shifted into the memory during the burn-in process to aid in toggling logic states of the chip elements.

Abstract: An apparatus and method which verify a system including a microprocessor. The apparatus includes first and second simulators which verify a target architecture using a test program and a functional description of the system, respectively. The first and second simlators extract first event information that expresses a verification item relating to a specification of the system. Further, checkers compare results of verification run by the second simulator with results of verification run by the first simulator. The first and second simulators execute an identification of the verification item. The checkers further examine a coverage of the system on the basis of second event information extracted from the verification item with the first event information, if the results of the verification run by the first simulator match the results of the verification run by the second simulator. The second event information is annotation data that describes information on events based on a specification for the system.

Abstract: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

Abstract: A nozzle for ultrasound wound treatment comprising a main body with proximal and distal ends, a reservoir and valve. The proximal end of the nozzle being removably attached to an ultrasound transducer. The distal end of the nozzle being marginally close and coaxial to the free distal end of the ultrasound transducer. The body of the nozzle connected with liquid reservoir, which holds the wound treatment solution and delivers same to the free end of ultrasound tip directly or through a tube. The nozzle is provided with valve for controlling flow rate of wound treatment solution. The nozzle can mix different liquids or a liquid with a gas and deliver same to the wound surface. The nozzle can also be provided with trigger system for one hand use. The present invention is a device, using ultrasonic waves to create, direct and deliver liquid treatment spray to a wound surface.

Abstract: A method of inspecting a reticle for defining a circuit layer pattern. First, the circuit layer pattern is analyzed to obtain a circuit characterization, and then, an area of the reticle is categorized into a first region and a second region based on the circuit characterization. A test reticle image of the reticle and a baseline representation containing an expected pattern of the test reticle image are provided. The first region of the test reticle image is compared to the first region of the baseline representation by a first analysis, and the second region of the test reticle image is compared to the second region of the baseline representation by a second analysis. The first analysis differs from the second analysis and this difference is based on difference in the circuit characterization of the first and second regions.

Abstract: A tube for implantation into the eye for replacement conduction of aqueous humor from the chambers of the eyeball to the subconjunctival tissue and ultimately to the venous system is comprised of an elongated fluid conducting conduit having distal and proximate ends, a sidewall and an interior passageway and at least one longitudinally extending opening in the sidewall that exposes the interior passageway and at least one nidi-forming structure carried by the conduit and extending laterally therefrom to implement the formation of at least one aqueous filtration bleb in the tissue of the eyeball. In one embodiment, the tube also contains at least one releasable ligature circumscribing the conduit. In another embodiment, the tube also contains an anchor appended to the conduit to prevent it from migrating from its placement site.

Abstract: A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The microcode unit includes an instruction address input for receiving an instruction address, a control variable input for receiving a control variable corresponding to a current state of the microprocessor, a control signal input for receiving all of the control signals output by the microcode unit for an immediately preceding instruction, and a plurality of embedded logic circuits each dedicated for evaluating one unique type of instruction received by the microcode unit.

Abstract: The present invention is a balloon catheter used primarily in treatment and surgery for the purpose of dilating lesion sites such as strictures or blockages in passages in the human body. The balloon catheter of the present invention has a structure wherein a guide wire passing tubular member is deployed passing through the interior of the expansion body, and the outer surface of the tubular member and the expansion body are concentrically fused near the distal end of the catheter. This is a balloon catheter that is characterized by the fact that the Shore hardness of the material configuring the outermost surface of the tubular member is smaller than the Shore hardness of the material configuring the expansion body. It is therefore possible to flexibly adjust the tip portion formed by securing the expansion body and the guide wire passing tubular member.

Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating data in architecture or functional design, a conversion circuit generating means generates a data conversion circuit between the communication channel and each of the IPs with reference to the IP database.

Abstract: Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a user design into a single programmable circuit element. A plurality of functional blocks in a user design that can be combined are identified. The possible combinations of functional blocks can be sorted according to a gain function. The gain function can, for example, weigh routing delays caused by a combination. The most desirable combination is selected from the sorted list of possible combinations. The selected combination is checked to see if it is feasible in light of electrical and user-specified constraints. If the combination is feasible, the combination is performed. Combinations continue to be performed by selecting the most desirable combinations from the sorted list.

Abstract: The invention relates to a method for placing design components of an integrated circuit. A first site is selected. Other sites that are at maximum distances from already used sites may be selected. Components that have minimum connectivity to already placed components are selected. These components are used for preplacement. Preferably, the number of preplaced components is small. The rest of the design components are placed. An overlap ratio is computed. If the overlap ratio is above a predetermined value, the result is unplaced and additional components are preplaced. Another placement is performed. Overlap ratio is again computed. The steps of unplacing, adding preplaced components and computing overlap ratio are repeated until the overlap ratio falls below the predetermined value.

Abstract: Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit (“IC”) layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.

Abstract: A method is used to check the direct convertibility of integrated semiconductor circuits into alternating phase masks. This is done by explicitly localizing the phase conflicts occurring in the corresponding layout while solely using the technological requirements made of the design. The set of phase conflicts determined with the aid of this formalism is complete and minimal and thus proves to be an optimum starting point for methods for handling conflicts of this type.

Abstract: A self-contained delivery device for delivery a selected volume of stored electrolyte solution at selected time intervals is disclosed. The device includes a housing having a delivery port, a chamber containing an upstream supply reservoir for holding a quantity of electrolyte solution, a downstream delivery reservoir for receiving electrolyte solution from the supply reservoir and, disposed between the two reservoirs, a membrane having a plurality of flow-through channels extending between the two reservoirs. A pair of electrodes placed in the chamber on either side of the membrane and controlled by a controller contained within the housing for pumping selected quantities of the electrolyte solution at selected time intervals. The device includes a chamber, and a membrane disposed in said chamber and having a channel extending between an upstream chamber region, where the said channel has a selected minimum cross-sectional dimension in the range between 2 and 100 nm.

Abstract: A method for verifying a property of a complete model of a system under study includes abstracting at least some of the variables from the model so as to produce an abstract model of the system. Beginning with an initial state in a state space of the abstract model, an abstract path is found through the state space of the abstract model in accordance with the transition relation to a target state defined by the property. A subset of the abstracted variables is restored to the abstract model so as to produce an intermediate model of the system, and the property on the complete model is verified based on the intermediate model.