Abstract: A computer-aided method for parallel calculation of the operating point of electrical circuits has the circuit partitioned into a number of partitions in a first step, in which the charging method is used for the parallel calculation of the individual partitions.

Abstract: A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression circuit of the designers' choice into the pnpn structure to eliminate the latchup and/or noise concerns.

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with the directed graph to facilitate identification of input equivalences.

Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Abstract: A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the pinlist. Third, the superset pinout for the family of devices is created from said superset listing of pins to eliminate potential footprint variations within the family of devices. Fourth, each pin of the superset pinout associated with each member of the family of devices is marked.

Abstract: A method for synthesizing a register transfer level (RTL) based design employs a bottom-up approach to generate a final top-level design. The top-level design is divided into a plurality of sub-modules. Each of the sub-modules is then independently synthesized using an RTL based design approach and independently adapted to conform to timing requirements produced for each of the sub-modules using time budgets that are based on the top-level timing requirements. Once the sub-modules are synthesized and pass individual timing requirements specific for those sub-modules, the sub-modules are integrated to form a top-level design. The top-level design may then be verified for timing requirements and other formal requirements.

Abstract: A subcutaneous port catheter system includes a reservoir defining a chamber therein. The catheter system also includes a guide catheter attached to the reservoir. The guide catheter has a guide lumen and a distal guide orifice. The catheter system further includes an inner catheter attached to the reservoir. The inner catheter is positioned within the guide lumen and extends through the distal guide orifice. A method of advancing fluid into a blood vessel of a body of a patient is also disclosed.

Abstract: Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.

Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: A behavioral modeling technique that captures driver delay. The output characteristics of a typical driver are represented by two basic element types: switching and non-switching. Switching elements are functions of both time-varying and non-time-varying parameters, and non-switching elements are functions of non-time-varying parameters only. The outputs of these elements are characterized and tabulated by applying a DC voltage on the output of the driver and measuring the current through each element. The time-varying switching element are represent by time-controlled resistors. The invention provides a methodology to account for variations in input transition rate, supply voltage(s) or temperature.

Abstract: A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.

Abstract: A clock driver placement system and method are provided to place clock drivers in a standard cell block. In accordance with one aspect of the invention, a system is provided for placing clock drivers in a standard cell block. The system operates using logic that establishes an initial clock driver placement pattern, and logic that determines a number of clock drivers needed in the standard cell block to comply with a time specification. The system also includes a logic that adds clock drivers to the standard cell block using the initial clock driver placement pattern. In accordance with another aspect of the invention, a method establishes an initial clock driver placement pattern and determines a number of clock drivers needed in the standard cell block to comply with a time specification. Then, the clock drivers are added to the standard cell block using the initial clock driver placement pattern.

Abstract: A mode register is created during the design of a complex, multi-mode electronic circuit. The mode register may contain connections to various switches, clocks, multiplexers, or other portions of the circuit that may have settings necessary to operate the circuit in different modes. The mode register may be used during circuit simulation by setting the mode register to a certain setting when running a static timing analysis script or other type of circuit simulation. After the circuit design is completed and before manufacturing the circuit, the mode register is disabled or removed from the circuit.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.

Abstract: A redundancy detection unit refers to layout data stored in a data storage unit and reflecting completed automatic placement and routing to detect a redundant region in a region having a cell arranged therein. An automatic insertion unit inserts in the detected redundant region a capacitive cell having a capacitive component and free of logic. As such a voltage drop can be reduced in a region scarce of LSI wiring resources. Furthermore, increased wiring capacitance can be provided without increased LSI chip area.

Abstract: A computer-implemented method is disclosed for verifying signal via impedance. Properties of a signal via and of any other vias within a given distance of the signal via are read from a circuit design database. A target characteristic impedance value for the signal via is obtained. A characteristic impedance of the signal via is calculated based on the other vias. The signal via is flagged as having an incorrect characteristic impedance if the calculated characteristic impedance does not match the target characteristic impedance value.