Abstract: Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.

Abstract: An operating method of a storage device and a nonvolatile memory device determine whether a nonvolatile memory device performs a program operation on at least one of a plurality of pages. Either a program time stamp table, managed with program elapsed times of the plurality of pages, or an update count of the program time stamp table is updated, based on the determination result.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: Embodiments of the present invention provide methods, computer systems, and computer program products for adjusting allocation of a storage device. In one embodiment, a first part of the storage device is allocated to tiering storage, and a second part of the storage device is allocated to cache storage. Operating statuses of the first part and second part are collected. A performance measure of the first part is obtained based on the operating status of the first part, and a performance measure of the second part is obtained based on the operating status of the second part. Allocation of a capacity of the storage devices is adjusted between the first part and the second part based on the performance measures of the first part and the second part.

Abstract: The disclosed systems include features to mitigate a risk of data corruption attributable to unexpected power loss events. In particular, the disclosed system identifies and retrieves complement data associated with each received write command and stores the complement data in a non-volatile cache while the complement data is overwritten via execution of the write command.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: An erase method of a nonvolatile memory device is provided which includes receiving an erase request; selecting an erase mode of a memory block corresponding to the erase request, based on an access condition of the nonvolatile memory device managed by a memory controller; and controlling the nonvolatile memory device to erase the memory block according to the selected erase mode. The erase mode includes a fast erase mode of which an erase time for the memory block is shorter than a reference time and a slow erase mode of which an erase time for the memory block is longer than the reference time.

Abstract: An apparatus having an interface and a circuit is shown. The interface is configured to receive a request to access a memory. The request includes a hint. The circuit is configured to select a current one of a plurality of cache policies based on the hint. The current cache policy includes a number of current parameters ranging from some to all of a plurality of management parameters of a cache device. The circuit is further configured to cache data of the request based on the current cache policy.

Abstract: A method of managing a memory by an electronic device is provided. The method includes configuring a swap data amount per unit time, identifying an actual use amount of swap data, and comparing the identified actual use amount of the swap data with the configured swap data amount per unit time.

Abstract: A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus for transferring data, a control bus for transferring a command and address CAL, and first and second memory devices coupled to the data bus and the control bus. The controller controls the first and second memory devices through the data bus and the control bus, wherein the first and second memory devices have different values of the CAL, and wherein a difference of the CAL values is greater than or equal to a RAS to CAS delay time tRCD.