Abstract: There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

Abstract: Example control methods of hybrid storage are provided, which are applied to each HDD-type storage device and each SSD-type storage device in a storage system having one or more HDD-type storage devices and one or more SSD-type storage devices. Each HDD-type storage device in the storage system is connected to the SSD-type storage device. Each HDD-type storage device and each SSD-type storage device stores one or more data blocks respectively. Access information of each data block stored in a storage device is periodically acquired. A storage location of each data block in the storage system is adjusted according to the acquired access information of each data block. By using the technical solution of the present disclosure, the storage location of the data block is dynamically configured according to an access frequency so that advantages of different storage devices are fully utilized.

Abstract: A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.

Abstract: An operation processing device including: processors, first cache corresponding to each processors; and a second cache shared by the processors, wherein the second cache includes; a data retaining unit that retains data, a first information retaining unit that retains first management information of data in the first cache, a second information retaining unit that retains second management information of data in the data retaining unit, a classifying unit that classifies a request performed by referencing the first management information and not referencing the second management information as a first type request and classifies a request performed by referencing the second management information as a second type request, a second processing unit that references the second management information to perform the second type request, and a first processing unit that references the first management information and does not reference the second management information to perform the first type request.

Abstract: A system, method, and apparatus are provided for facilitating reverse reading of sequentially stored variable-length data records. Each record is stored with accompanying size metadata that identifies the size or length of the record. Further, if the length of a given record is greater than a threshold (e.g., 127 bytes when the length is stored with variable-length quantity encoding), such that more than one byte (or other storage unit) is needed to store the record length, an additional byte (or other unit) is configured to store the size/length of the record length (e.g., the number of bytes required to store the record length). The most significant bit of the additional byte is set to 1, so that during reverse reading, the location and size of the record length value can be quickly determined.

Abstract: A method of data separation includes receiving a host write command operation, identifying temperature of data contained in memory blocks during the host write command operation, selecting a victim block of the memory blocks based on the identified temperature, moving data from the victim block to a destination block, and assigning a sequence number to the destination block when the destination block is full.

Abstract: An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. The synchronizer may synchronize the first address in response to the clock at a preset time point before the second address is generated by the address generator, and output the synchronized address as an output address.

Abstract: A cache management system and method allowing data stored in non-sequential storage blocks on a storage system to be retrieved to a cache memory in advance of a call for the data based on a defined event in a host. The system and method detects a defined event from the host. The defined event issues an event read sequence of read requests for data from non-sequential storage blocks of a storage system. The event data read sequence of read requests is recorded to create a pre-fetch list. The read requests in the event read sequence are then issued for the pre-fetch list associated with the defined event to store the requested data in the cache memory.

Abstract: A mass data storage system includes a number of communicatively coupled storage drives powered by one or more power supplies. Shared control electronics selectively connect power and a data signal to a select storage drive via instructions within a control signal received by the common controller. Instructions for selectively powering and connecting the data signal are transmitted over a first signal path to a first controller of the shared electronics. Responsive to successful execution of the instructions, a drive access command is sent over a second different signal path to a second controller of the shared electronics.

Abstract: In a storage system, a control device determines that at least one first storage device of X storage devices is out of service. Then, the control device selects a second storage device from the X storage device. A quantity of stripe members of a data stripe stored in the second storage device is less than a ratio of T divided by X. The control device further writes target data into the second storage device. The target data is a data unit or a check unit used to update at least one stripe member of the data stripe stored in the first storage device.

Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.

Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.

Abstract: According to one or more embodiments of the disclosure, systems and methods for reducing power consumption in a memory architecture are provided. In one embodiment, a method may include determining a transition from a first power state to a second power state. The method may also include determining, using a page location identifier to access a page location table, a first dirty memory page indication. Furthermore, the method may include copying data stored in a first memory location in a volatile memory corresponding to the page location identifier to a second memory location in a non-volatile memory corresponding to the page location identifier. The method may also include deactivating the volatile memory.

Abstract: A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss, determine, as an update candidate, a piece of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract: Systems and methods for data storage management technology that enables a guest module of a virtual machine to indicate an order in which a host module should write data from physical memory to a secondary storage. An example method may comprise: identifying, by a processing device executing a host module, a plurality of modifications to physical memory made by a plurality of direct access operations executed by a guest module of a virtual machine; determining, by the host module, an order of the plurality of modifications to physical memory; receiving, by the host module, a synchronization request from the guest module; and responsive to the synchronization request, copying, by the host module, data from the physical memory to a secondary storage in view of the order of the plurality of modifications.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.

Abstract: A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory comprising a plurality of NVM lines.

Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.